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rev.1.02 may 25, 2007 page 1 of 124 rej03b0179-0102 description the 4571 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with three 8-bit timers (each timer has one or two reload registers), interrupts, and vo ltage drop detection circuit. the various microcomputers in the 4571 group include variations of the built-in memory size as shown in the table below. features ? minimum instruction execution time..............................0.5 s (at 6 mhz oscillation frequency, in through-mode) ? supply voltage ........ ........... ........... ........... ............ ..1.8 to 5.5 v (it depends on os cillation frequency and operation mode) ?timers timer 1..................................8-bit timer with a reload register and carrier wave outpu t auto-control function timer 2..................................8-bit timer with a reload register timer 3..................... 8-bit timer with two reload registers and carrier wave ge neration circuit ? interrupt ..................................................................... 6 sources ? key-on wakeup function pins .............................................. 12 ? i/o port ................................................................................. 17 ? output port ............................................................................. 1 ? input port ............. ........... ........... ........... ......... ......... ......... ....... 1 ? voltage drop detection circuit reset occurrence................................typ. 1.65 v (ta = 25 c) reset release ......................................typ. 1.75 v (ta = 25 c) interrupt occurrence...........................typ. 1.85 v (ta = 25 c) ? watchdog timer ? power-on reset circuit ? clock generating circui t (ceramic resonator) application remote control transmitter note 1.shipped in blank table 1 support product part number rom size ( 10 bits) ram size ( 4 bits) package rom type m34571g4fp (note 1) 4096 words 128 words prsp0024ga-a qzrom m34571g4-xxxfp 4096 words 128 words prsp0024ga-a qzrom m34571g6fp (note 1) 6144 words 128 words prsp0024ga-a qzrom m34571g6-xxxfp 6144 words 128 words prsp0024ga-a qzrom m34571gdfp (note 1) 16384 words 128 words prsp0024ga-a qzrom m34571gd-xxxfp 16384 words 128 words prsp0024ga-a qzrom 4571 group single-chip 4-bit cmos microcomputer rej03b0179-0102 rev.1.02 may 25, 2007
rev.1.02 may 25, 2007 page 2 of 124 rej03b0179-0102 4571 group pin configuration fig 1. pin configuration (prsp0024ga-a type) outline: prsp0024ga-a (24p2q-a) pin configuration (top view) 12 p1 1 p1 2 11 p1 0 p1 3 10 p0 3 p2 0 /int0 9 p0 2 p2 1 /int1 8 p0 1 13 p3 0 7 p0 0 14 p3 1 6 15 d 0 reset k 5 16 d 1 x out 4 17 d 2 x in 3 18 d 3 v ss 2 19 d 4 /cntr0 1 v dd 20 c/cntr1 21 22 23 24 m34571gxfp m34571gx-xxxfp
rev.1.02 may 25, 2007 page 3 of 124 rej03b0179-0102 4571 group functional block fig 2. functional block diagram (prsp0024ga-a type) ram 128 words 4 bits rom 4096, 6144, 16384 words 10 bits memory i/o port internal peripheral functions timer timer 1 (8 bits) timer 2 (8 bits) timer 3 (8 bits) 4500 series cpu core register a (4 bits) register b (4 bits) register d (3 bits) register e (8 bits) stack register sk (8 levels) interrupt stack register sdp (1 level) alu (4 bits) watchdog timer (16 bits) port p0 4 port p1 4 port p2 2 port d 5 system clock generating circuit x in -x out (ceramic) voltage drop detection circuit port p3 2 port c 1 port k 1 power-on reset circuit
rev.1.02 may 25, 2007 page 4 of 124 rej03b0179-0102 4571 group performance overview table 2 performance overview parameter function number of basic instructions m34571g4/g6 126 m34571gd 128 minimum instruction execution time 0.5 s (oscillation frequency 6 mhz: through mode) memory sizes rom m34571g4 4096 words 10 bits m34571g6 6144 words 10 bits m34571gd 16384 words 10 bits ram 128 words 4 bits i/o port d 0? d 4 i/o (input is examined by skip decision) five independent i/o ports; the output structure of ports d 0? d 3 is switched by software. port d 4 is also used as cntr0, respectively. p0 0 ? p0 3 i/o 4-bit i/o port; a pull-up function and a key-on wakeup function can be switched by software. p1 0 ? p1 3 i/o 4-bit i/o port; a pull-up function and a key-on wakeup function can be switched by software. p2 0 , p2 1 i/o 2-bit i/o port; a pull-up function and a key-on wakeup function can be switched by software. ports p2 0 and p2 1 are also used as int0 and int1, respectively. p3 0 , p3 1 i/o 2-bit i/o port ; the output structure is switched by software. c output 1-bit output port (cmos output only); port c is also used as cntr1 pin. k input 1-bit input port ; a key-on wakeup function can be switched by software. cntr0 timer i/o 1-bit i/o port ; cntr0 pin is also used as port d 4 . cntr1 timer output 1-bit output port ; cntr1 pin is also used as port c. int0, int1 interrupt input 1-bit input port ; int0 and int1 are also used as ports p2 0 and p2 1 , respectively. timer timer 1 8-bit timer with a reload register and carrier wave output auto-control function, and has an event counter. timer 2 8-bit timer with a reload register. timer 3 8-bit timer with two reload regist ers and carrier wave generation function. watchdog timer 16-bit timer, fixed di viding frequency (timer for monitor) power-on reset circuit built-in voltage drop detection circuit reset occurrence typ. 1.65 v (ta=25 c) reset release typ. 1.75 v (ta=25 c) interrupt occurrence typ. 1.85 v (ta=25 c) interrupt source 6 sources (two for external, three for timers, voltage drop detection circuit) nesting 1 level subroutine nesting 8 levels device structure cmos sillicon gate package 24-pin plastic mo lded ssop (prsp0024ga-a) operating temperature range -20 to 85 c power source voltage 1.8 to 5.5 v (it depends on oscillation frequenc y and operation mode) power dissipation (typ. value) at active mode 0.3 ma (ta = 25 c, v dd = 3.0 v, f(x in )=4 mhz, f(stck)=f(x in )/8) at ram back-up 0.1 a (ta = 25 c, output transistor is cut-off state)
rev.1.02 may 25, 2007 page 5 of 124 rej03b0179-0102 4571 group pin description multifunction note 1.pins except above have just single function. note 2.the input of d 4 can be used even when cntr0 (output) is selected. the input/output of d 4 can be used even when cntr0 (input) is selected. be careful when using inputs of both cntr0 and d 4 since the input threshold value of cntr 0 pin is different from that of port d 4 . note 3.?h? output function of port c can be used even when the cntr1 (output) is used. note 4.the input/output of p2 0 can be used even when int0 is used. be careful when using inputs of both int0 and p2 0 since the input threshold value of int0 pin is different from that of port p2 0 . note 5.the input/output of p2 1 can be used even when int1 is used. be careful when using inputs of both int1 and p2 1 since the input threshold value of int1 pin is different from that of port p2 1 . table 3 pin description pin name input/output function v dd power source ? connected to a plus power supply. v ss power source ? connected to a 0 v power supply. reset reset i/o i/o an n-channel open-drain i/o pin for a system reset. when the srst instruction, watchdog timer, or the built-in power-on reset causes the system to be reset, the reset pin outputs ?l? level. x in main clock input input i/o pins of the main clock gener ating circuit. connect a cera mic resonator between pins x in and x out . a feedback resistor is built-in between them. x out main clock output output d 0 ? d 4 i/o port d (input is examined by skip decision.) i/o each pin of port d has an independent 1-bit wide i/o function. the output structure of ports d 0? d 3 can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ?1? and select the n-channel open-drain. port d 4 is also used as cntr0 pin. p0 0 ? p0 3 i/o port p0 i/o port p0 serves as a 4-bit i/o port. the output structure is n-channel open-drain. port p0 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p1 0 ? p1 3 i/o port p1 i/o port p1 serves as a 4-bit i/o port. the output structure is n-channel open-drain. port p1 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p2 0 , p2 1 i/o port p2 i/o port p2 serves as a 2-bit i/o port. the output structure is n-channel open-drain. for input use, set the latch of the specified bit to ?1?. ports p2 0 and p2 1 are also used as int0 pin and int1 pin, respectively. p3 0 , p3 1 i/o port p3 i/o port p3 serves as a 2-bit i/o port. the output structure can be switched to n- channel open-drain or cmos by software. for input use, set the latch of the specified bit to ?1?. c output port c output port c serves as a 1-bit output port. the output structure is cmos. port c is also used as cntr1. k input port k input port k serves as a 1-bit input port. it has the key-on wakeup function which can be switched by software. when port k is used for the input of key matrix, connect a pull-up resistor to it externally. cntr0, cntr1 timer i/o i/o cntr0 pin has the function to input t he clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. cntr1 pin has the function to outpu t the pwm signal generated by timer 3. cntr0 pin and cntr1 pin are also used as ports d 4 and c, respectively. int0, int1 interrupt input input int0 pin and int1 pin accept external interrupts. they have the key-on wakeup function which can be switched by software. int0 pin and int1 pin are also used as ports p2 0 and p2 1 , respectively. table 4 pin description pin multifunction pin multifunction pin multifunction pin multifunction c cntr1 p2 0 int0 cntr1 c int0 p2 0 d 4 cntr0 p2 1 int1 cntr0 d 4 int1 p2 1
rev.1.02 may 25, 2007 page 6 of 124 rej03b0179-0102 4571 group port function definition of clock and cycle ? operation source clock the operation source clock is th e source clock to operate this product. in this product, the following clocks are used. ? clock (f(x in )) by the external ceramic resonator ? clock (f(x in )) by the external input ? system clock the system clock is the basic cl ock for controlling this product. the system clock is selected by the register mr. ? instruction clock the instruction clock is a signa l derived by dividing the system clock by 3. the one instruction clock cycle generates the one machine cycle. ? machine cycle the machine cycle is the standard cycle required to execute the instruction. note 1.the frequency divided by 8 is selected after system is released from reset. table 5 port function port pin input output output structure i/o unit control instructions control registers remark port d d 0 ? d 3 i/o (5) n-channel open-drain/ cmos 1 bit sd, rd szd, cld fr1 programmable output structure selection function d 4 /cntr0 n-channel open-drain w1 w2 w5 ? port p0 p0 0 p0 1 p0 2 p0 3 i/o (4) n-channel open-drain 4 bits op0a iap0 pu0 k0 programmable pull-up and key-on wakeup function port p1 p1 0 p1 1 p1 2 p1 3 i/o (4) n-channel open-drain 4 bits op1a iap1 pu1 k1 programmable pull-up and key-on wakeup function port p2 p2 0 /int0 p2 1 /int1 i/o (2) n-channel open-drain 2 bits op2a iap2 pu2 k2, i1, i2, l1 programmable pull-up and key-on wakeup function port p3 p3 0 p3 1 i/o (2) n-channel open-drain/ cmos 2 bits op3a iap3 fr0 programmable output structure selection function port c c/cntr1 output (1) cmos 1 bit rcp scp w1, w3, w5 ? port k k input (1) - 1 bit iak k2 programmable key-on wakeup function table 6 table selection of system clock register mr system clock operation mode mr 3 mr 2 1 1 f(stck) = f(x in )/8 frequency divided by 8 mode 1 0 f(stck) = f(x in )/4 frequency divided by 4 mode 0 1 f(stck) = f(x in )/2 frequency divided by 2 mode 0 0 f(stck) = f(x in ) frequency through mode
rev.1.02 may 25, 2007 page 7 of 124 rej03b0179-0102 4571 group connections of unused pins note 1.if a port input instruction (szd, iap0, iap1, iap2, iap3) is executed when the output latch is 1, the supply voltage may be increased in the instruction execution cycle by the through current. note 2.do not select the cntr0 input as the timer 1 count source. (w1 1 w1 0 11) note 3.set the input of int0 pin or int1 pin to be disabled. (i1 3 =0, i2 3 =0) note 4.set the output of the cntr1 pin to be invalid. (w3 3 =0) (note when connecting to v ss or v dd ) connect the unused pins to v ss using the thickest wire at the shortest distance against noise. table 7 port function pin connection usage condition output structure pull-up transistor key-on wakeup value of output latch others d 0 ? d 3 p3 0 , p3 1 open. n-channel open-drain ?? 0/1 (note 1) cmos ?? 0/1 ? connect to v ss . n-channel open-drain ?? 0/1 ? cmos ?? 0 ? connect to v dd . n-channel open-drain ?? 1 ? cmos ?? 1 ? d 4 /cntr0 open. n-channel open-drain ?? 0/1 (notes 1, 2) connect to v ss . n-channel open-drain ?? 0/1 (note 2) connect to v dd . n-channel open-drain ?? 1 (note 2) p0 0 ? p0 3 , p1 0 ? p1 3 open. n-channel open-drain off invalid 0/1 (note 1) on invalid 1 ? connect to v ss . n-channel open-drain off invalid 0/1 ? connect to v dd . n-channel open-drain on/off valid/invalid 1 ? p2 0 /int0 p2 1 /int1 open. n-channel open-drain off invalid 0/1 (notes 1, 3) on invalid 1 (note 3) connect to v ss . n-channel open-drain off invalid 0/1 (note 3) connect to v dd . n-channel open-drain on/off valid/invalid 1 (note 3) c/cntr1 open. cmos ?? 0/1 ? connect to v ss .cmos ?? 0 (note 4) k connect to v ss . ?? invalid ?? connect to v dd . ?? valid/invalid ??
rev.1.02 may 25, 2007 page 8 of 124 rej03b0179-0102 4571 group port block diagram fig 3. port block diagram (1) register y decoder skip decision szd instruction sd instruction rd instruction cld instruction fr1 i (note 3) (note 1) (note 1) d 0 - d 3 (note 2) s r q notes 1. this symbol represents a par asitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. i represents bits 0 to 3. 4. a falling edge of port input is detected. (note 1) (note 1) d 4 /cntr0 (note 2) clock input for timer 1 event count w5 2 0 1 w1 0 w1 1 register y decoder skip decision szd instruction sd instruction rd instruction cld instruction s r q w5 0 0 1 1/2 w2 3 0 1 timer 1 underflow signal timer 2 underflow signal edge detection circuit key-on wakeup input iap0 instruction op0a instruction (note 1) (note 1) p0 0 - p0 3 (note 2) d t q k0 i pu0 i a i register a a i (note 3) (note 3) (note 4) (note 3) pull-up transistor
rev.1.02 may 25, 2007 page 9 of 124 rej03b0179-0102 4571 group fig 4. port block diagram (2) edge detection circuit key-on wakeup input iap1 instruction op1a instruction (note 1) (note 1) p1 0 - p1 3 (note 2) d t q k1 i pu1 i a i register a a i (note 3) (note 3) (note 4) (note 3) pull-up transistor iap2 instruction op2a instruction (note 1) (note 1) pu2 0 p2 0 /int0(note 2) d t q external 0 interrupt external 0 interrupt key-on wakeup input timer 1 count start synchronous circuit input (notes 5, 6) a 0 register a a 0 edge detection circuit key-on wakeup input k2 0 (note 4) iap2 instruction op2a instruction (note 1) (note 1) pu2 1 p2 1 /int1(note 2) d t q external 1 interrupt external 1 interrupt key-on wakeup input a 1 register a a 1 edge detection circuit key-on wakeup input k2 1 (note4) pull-up transistor pull-up transistor (notes 5, 6) notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. i represents bits 0 to 3. 4. falling edge of port input is detected. 5. as for details, refer to the external interrupt structure. 6. the threshold value of port input is different from that of external interrupt input.
rev.1.02 may 25, 2007 page 10 of 124 rej03b0179-0102 4571 group fig 5. port block diagram (3) iap3 instruction op3a instruction (note 1) (note 1) p3 0, p3 1 (note 2) d t q a j register a a j (note 3) fr0 j (note 3) (note 1) (note1) c/cntr1(note 2) d t q scp instruction rcp instruction s r r q pwmod timer 1 underflow signal w5 1 w1 2 carrier wave output auto-control signal pwmout (note 1) k(note 2) edge detection circuit key-on wakeup input k2 2 (note 4) register a a 0 iak instruction notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. j represents bits 0 or 1. 4. falling edge of port input is detected.
rev.1.02 may 25, 2007 page 11 of 124 rej03b0179-0102 4571 group fig 6. port block diagram (4) key-on wakeup input snzi0 instruction (note 1) l1 1 0 1 edge detection circuit level detection circuit p2 0 /int0 i1 3 i1 2 falling 0 1 rising l1 0 i1 1 0 1 one-sided edge detection circuit both edges detection circuit skip exf0 external 0 interrupt timer 1 count start synchronization circuit input (note 2) (note 3) note 1: this sym bol represents a parasitic diode on the port. 2: when ix 2 = 0(x=0 or 1) is 0, ?l? level is detected. when ix 2 is 1, ?h? level is detected. 3: when ix 2 is 0, falling edge is detected. when ix 2 is 1, rising edge is detected. (note 1) key-on wakeup input snzi1 instruction (note 1) l1 3 0 1 edge detection circuit level detection circuit p2 1 /int1 i2 3 i2 2 falling 0 1 rising l1 2 i2 1 0 1 one-sided edge detection circuit both edges detection circuit skip exf1 external 1 interrupt (note 2) (note 3) (note 1)
rev.1.02 may 25, 2007 page 12 of 124 rej03b0179-0102 4571 group function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4-bit data addition, comparison , and operation, or operation, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, exchange, and i/o operation. carry flag cy is a 1-bit flag that is set to ?1? when there is a carry with the amc instruction (figure 7). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (figure 8). carry flag cy can be set to ?1? with the sc instruction and cleared to ?0? with the rc instruction. (3) registers b and e register b is a 4-bit register us ed for temporary storage of 4-bit data, and for 8-bit data transf er together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 9). register e is undefined after syst em is released from reset and returned from the ram back-up. accordingly, set the initial value. (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruct ion is executed (figure 10). also, when the tabp p instruction is executed at uptf flag = ?1?, the high-order 2 bits of rom reference data is stored to the low-order 2 bits of regi ster d, the high-order 1 bit of register d is ?0?. when the tabp p instruction is executed at uptf flag = ?0?, the contents of register d remains unchanged. the uptf flag is set to ?1? with the supt instruction and cleared to ?0? with the rupt instruction. the initial value of uptf flag is ?0?. register d is undefined after syst em is released from reset and returned from the ram back-up. accordingly, set the initial value. fig 7. amc instruction execution example fig 8. rar instruction execution example fig 9. registers a, b and register e fig 10. tabp p instruction execution example (cy) (m(dp)) (a) addition alu rc instruction sc instruction cy a 3 a 2 a 1 a 0 rar instruction a 0 cy a 3 a 2 a 1 a 3 a 2 a 1 a 0 register a tab instruction e 3 e 2 e 1 e 0 e 7 e 6 e 5 e 4 b 3 b 2 b 1 b 0 register b teab instruction register e a 3 a 2 a 1 a 0 register a tba instruction b 3 b 2 b 1 b 0 register b tabe instruction a 3 a 2 a 1 a 0 dr 2 dr 1 dr 0 pc l register a (4) low-order 4bits register d (3) high-order 2 bits register b (4) middle-order 4 bits rom immediate field value p the contents of register d the contents of register a specifying address tabp p instruction * flag uptf = 1; high-order 2 bits of reference data is transferred to the low-order 2 bits of register d. ?0? is stored to the high-order 1 bit of register d. flag uptf = 0; data is not transferred to register d. p 3 p 2 p 1 p 0 p 6 p 5 p 4 pc h 840
rev.1.02 may 25, 2007 page 13 of 124 rej03b0179-0102 4571 group (5) stack registers (sks) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; ? branching to an interrupt service routine (referred to as an interrupt service routine), ? performing a subroutine call, or ? executing the table refere nce instruction (tabp p). stack registers (sks) are eight identical registers, so that subroutines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be careful not to over the stack when performing these operations together. the contents of registers sks are destroyed when 8 levels are exceeded. the register sk nesting level is pointed automatically by 3-bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 11 shows the stack registers (sks) structure. figure 12 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an interrupt occurs, this register (s dp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and register b just before an interr upt until returning to the original routine. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table reference instruction. (7) skip flag skip flag controls skip deci sion for the conditional skip instructions and cont inuous described skip instructions. when an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. fig 11. stack registers (sks) structure fig 12. example of operation at subroutine call stack pointer (sp) points ?7? at reset or returning from ram back-up mode. it points ?0? by executing the first bm instruction, and the contents of program counter is stored in sk 0 . when the bm instruction is executed after eight stack registers are used ((sp) = 7), (sp) = 0 and the contents of sk 0 is destroyed. program counter (pc) sk 0 sk 1 sk 2 sk 3 sk 4 sk 5 sk 6 sk 7 executing bm instruction executing rt instruction (sp) = 0 (sp) = 1 (sp) = 2 (sp) = 3 (sp) = 4 (sp) = 5 (sp) = 6 (sp) = 7 (sp) 0 (sk 0 ) 0001 16 (pc) sub1 (pc) (sk 0 ) (sp) 7 main program address 0000 16 nop 0001 16 bm sub1 0002 16 nop sub1: nop rt subroutine note : returning to the bm instruction execution address with the rt instruction, and the bm instruction becomes the nop instruction.
rev.1.02 may 25, 2007 page 14 of 124 rej03b0179-0102 4571 group (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a bi nary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call inst ructions, return instructions, or the table reference instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which specifies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 13). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, register x specifies a file, and register y specifies a ram digit (figure 14). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd , or szd instruction (figure 15). ? note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig 13. program counter (pc) structure fig 14. data pointer (dp) structure fig 15. sd instruction execution example a 3 a 2 a 1 a 0 a 6 a 5 a 4 pc h specifying page program counter p 3 p 2 p 1 p 0 p 6 p 5 p 4 pc l specifying address register y (4) data pointer (dp) x 2 x 1 x 0 y 3 z 1 z 0 x 3 y 2 y 1 y 0 register x (4) register z (2) specifying ram digit specifying ram file specifying ram file group specifying bit position 0 0 0 1 register y (4) set d 3 d 2 1 d 1 d 0 port d output latch
rev.1.02 may 25, 2007 page 15 of 124 rej03b0179-0102 4571 group program memory (rom) the program memory is a mask rom. 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. figure 16 shows the rom map of m34571g6. note 1.data in pages 64 to 127 can be referred with the tabp p instruction after the sbk instruction is executed. data in pages 0 to 63 can be referred with the tabp p instruction after the rbk instruction is executed. a part of page 1 (addresses 0080 16 to 00ff 16 ) is reserved for interrupt addresses (figure 17). when an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and th e instruction at the interrupt address is executed. when usin g an interrupt service routine, write the instruction generating th e branch to that routine at an interrupt address. page 2 (addresses 0100 16 to 017f 16 ) is the special page for subroutine calls. subroutines writ ten in this page can be called from any page with the 1-word instruction (bm). subroutines extending from page 2 to another pa ge can also be called with the bm instruction when it starts on page 2. rom pattern (bits 9 to 0) of al l addresses can be used as data areas with the tabp p instruction. rom code protect address when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by renesas technology corp., read ing or writing from/to qzrom is disabled by a serial programmer. as for the qzrom product in blan k, the rom code is protected by selecting the protect bit wr ite at rom writing with a serial programmer. as for the qzrom product shippe d after writing, whether the rom code protect is used or not can be selected as rom option setup (?mask option? written in the mask file converter) when ordering. fig 16. rom map of m34571gd fig 17. page 1 (addresses 0080 16 to 00ff 16 ) structure table 8 rom size and pages part number rom (prom) size ( 10 bits) pages m34571g4 4096 words 32 (0 to 31) m34571g6 6144 words 48 (0 to 47) m34571gd 16384 words 128 (0 to 127) interrupt address page subroutine special page 0000 16 007f 16 0080 16 00ff 16 0100 16 017f 16 0180 16 3fff 16 page 127 page 0 page 1 page 2 page 3 9876543210 00ff 16 008c 16 008a 16 0088 16 0086 16 0084 16 0082 16 0080 16 9876543210 008e 16 voltage drop detection circuit interrupt address timer 2 interrupt address timer 1 interrupt address external 0 interrupt address external 1 interrupt address timer 3 interrupt address
rev.1.02 may 25, 2007 page 16 of 124 rej03b0179-0102 4571 group data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram (also, set a value after system returns from ram back-up). table 9 shows the ram size. figure 18 shows the ram map. ? note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig 18. ram map table 9 ram size and pages part number ram size m34571g4 128 words 4 bits (512 bits) m34571g6 m34571gd register z register y register x 0 0 1 2 3 ... 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ram 128 words 4 bits (512 bits) 128 words 4 bits (512 bits) m34571g4 m34571g6 m34571gd z=0 x=0 to 7 y=0 to 15
rev.1.02 may 25, 2007 page 17 of 124 rej03b0179-0102 4571 group interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt addr ess) according to each interrupt source. an interrupt occurs when the foll owing 3 cond itions are satisfied. ? an interrupt activated condition is satisfied (request flag = ?1?) ? interrupt enable bit is enabled (?1?) ? interrupt enable flag is enabled (inte = ?1?) table 10 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (in te) controls whether the every interrupt enable/disable. interrupts are enabled when inte flag is set to ?1? with the ei instru ction and disabled when inte flag is cleared to ?0? with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to ?0,? so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bit use an interrupt enable bit of interrupt control registers v1 and v2 to select the corresponding interrupt or skip instruction. table 11 shows the interrupt reques t flag, interrupt enable bit and skip instruction. table 12 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to ?1.? each interrupt request flag except the voltage dr op detection circuit interrupt request flag is cleared to ?0? when either; ? an interrupt occurs, or ? the next instruction is ski pped with a skip instruction. the voltage drop detection circu it interrupt request flag cannot be cleared to ?0? at the state that the activated condition is satisfied. each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the inte flag or its interrupt enable bit. once set, the interrupt request flag retains set until a clear condition is satisfied. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one inte rrupt request flag is set when the interrupt disable state is released, the interru pt priority leve l is as follows shown in table 10. table 10 interrupt sources priority level interrupt source interrupt address interrupt name activated condition 1 voltage drop detection circuit interrupt when supply voltage goes lower than specified value address e in page 1 2 external 0 interrupt level change of int0 pin address 0 in page 1 3 external 1 interrupt level change of int1 pin address 2 in page 1 4 timer 1 interrupt timer 1 underflow address 4 in page 1 5 timer 2 interrupt timer 2 underflow address 6 in page 1 6 timer 3 interrupt timer 3 underflow address 8 in page 1 table 11 interrupt request flag, interrupt enable bit and skip instruction interrupt name interrupt request flag skip instruction interrupt enable bit voltage drop detection circuit interrupt vdf snzvd v2 3 external 0 interrupt exf0 snz0 v1 0 external 1 interrupt exf1 snz1 v1 1 timer 1 interrupt t1f snzt1 v1 2 timer 2 interrupt t2f snzt2 v1 3 timer 3 interrupt t3f snzt3 v2 0 table 12 interrupt en able bit function interrupt enable bit occurrence of interrupt skip instruction 1 enabled invalid 0 disabled valid
rev.1.02 may 25, 2007 page 18 of 124 rej03b0179-0102 4571 group (4) internal state during an interrupt the internal state of the microcom puter during an interrupt is as follows (figure 20). ? program counter (pc) an interrupt address is set in program c ounter. the address to be executed when returnin g to the main routine is automatically stored in the stack register (sk). ? interrupt enable flag (inte) inte flag is cleared to ?0? so that interrupts are disabled. ? interrupt request flag only the request flag for the curre nt interrupt source is cleared to ?0? (the voltage drop detecti on circuit interrupt request flag is excluded) ? data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt o ccurs, a program at an interrupt address is executed after branching a data store sequence to stack register. write the branch instruction to an interrupt service routine at an interrupt address. use the rti instruction to return from an interrupt service routine. interrupt enabled by executing th e ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interr upts are enabled after returning the main routine. (refer to figure 19) fig 19. program example of interrupt processing fig 20. internal state when interrupt occurs fig 21. interrupt system diagram main routine interrupt occurs interrupt is enabled interrupt service routine ei rti : interrupt enabled state : interrupt disabled state each interrupt address ? program counter (pc) the address of main routine to be executed when returning ? stack register (sk) 0 (interrupt disabled) ? interrupt enable flag (inte) 0 (excluding voltage drop detection interrupt request flag) ? interrupt request fl ag (only the flag fo r the current interrupt source) stored in the interrupt stack register (sdp) automatically ? data pointer, carry flag, registers a and b, skip flag exf0 request flag (state retained) v1 0 enable bit enable flag address 0 in page 1 int0 pin interrupt waveform input timer 2 underflow t1f v1 2 address 4 in page 1 timer 1 underflow t2f v1 3 address 6 in page 1 t3f v2 0 address 8 in page 1 activated condition inte timer 3 underflow exf1 v1 1 address 2 in page 1 int1 pin interrupt waveform input vdf v2 3 address e in page 1 when supply voltage goes lower than specified value
rev.1.02 may 25, 2007 page 19 of 124 rej03b0179-0102 4571 group (6) interrupt control registers ? interrupt control register v1 interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register v1. se t the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. ? interrupt control register v2 the voltage drop detecti on circuit interrupt en able bit and timer 3 interrupt enable bit are assigned to register v2. set the contents of this register through register a with the tv2a instruction. the tav2 instruction can be used to transfer the cont ents of register v2 to register a. note 1.?r? represents read enabled, and ?w? represents write enabled. table 13 interrupt control registers interrupt control register v1 at reset : 0000 2 at ram back-up : 0000 2 r/w tav1/tv1a v1 3 timer 2 interrupt enable bit 0 interrupt disabled (snzt2 instruction is valid) 1 interrupt enabled (snzt2 instruction is invalid) v1 2 timer 1 interrupt enable bit 0 interrupt disabled (snzt1 instruction is valid) 1 interrupt enabled (snzt1 instruction is invalid) v1 1 external 1 interrupt enable bit 0 interrupt disabled (snz1 instruction is valid) 1 interrupt enabled (snz1 instruction is invalid) v1 0 external 0 interrupt enable bit 0 interrupt disabled (snz0 instruction is valid) 1 interrupt enabled (snz0 instruction is invalid) interrupt control register v2 at reset : 0000 2 at ram back-up : 0000 2 r/w tav2/tv2a v2 3 voltage drop detector interrupt enable bit 0 interrupt disabled (snzvd instruction is valid) 1 interrupt enabled (snzvd instruction is invalid) v2 2 not used 0 this bit has no function, but read/write is enabled. 1 v2 1 not used 0 this bit has no function, but read/write is enabled. 1 v2 0 timer 3 interrupt enable bit 0 interrupt disabled (snzt3 instruction is valid) 1 interrupt enabled (snzt3 instruction is invalid)
rev.1.02 may 25, 2007 page 20 of 124 rej03b0179-0102 4571 group (7) interrupt sequence interrupts only occur when th e respective inte flag, interrupt enable bits (v1 0 ? v1 3 , v2 0 , v2 3 ), and interrupt request flag are ?1. ? the interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. the interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (refer to figure 22). fig 22. interrupt sequence t 3 t 2 t 1 1 machine cycle system clock (stck) interrupt enable flag (inte) int0 int1 t1f t2f t3f the program starts from the interrupt address. interrupt activated condition is satisfied. flag cleared 2 to 3 machine cycles (notes 1, 2) exf0 exf1 external 0, external 1 interrupt timer 1 timer 2 timer 3 interrupt vdf voltage drop detection circuit interrupt when an interrupt request flag is set after its interrupt is enabled ei instruction execution cycle interrupt enabled state interrupt disabled state retaining level of system clock for 4 periods or more is necessary. notes 1: the address is stacked to the last cycle. 2: this interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. t 3 t 2 t 1 t 3 t 2 t 1 t 3 t 2 t 1 t 2 t 1
rev.1.02 may 25, 2007 page 21 of 124 rej03b0179-0102 4571 group external interrupts the 4571 group has the external 0 interrupt and external 1 interrupt. an external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). the external interrupt can be cont rolled with the interrupt control registers i1 and i2. fig 23. external interrupt circuit structure table 14 external interrupt activated conditions name input pin activated condition valid waveform selection bit external 0 interrupt p2 0 /int0 when the next waveform is input to p2 0 /int0 pin ? falling waveform ( ? h ? ? l ? ) ? rising waveform ( ? l ? ? h ? ) ? both rising and falling waveforms i1 1 i1 2 external 1 interrupt p2 1 /int1 when the next waveform is input to p2 1 /int1 pin ? falling waveform ( ? h ? ? l ? ) ? rising waveform ( ? l ? ? h ? ) ? both rising and falling waveforms i2 1 i2 2 key-on wakeup input snzi0 instruction (note 1) l1 1 0 1 edge detection circuit level detect ion circuit p2 0 /int0 i1 3 i1 2 falling 0 1 rising l1 0 i1 1 0 1 one-sided edge detection circuit both edges detection circuit skip exf0 external 0 interrupt timer 1 count start synchronization circuit input (note 2) (note 3) note 1: this sym bol represents a parasitic diode on the port. 2: when ix 2 = 0(x=0 or 1) is 0, ?l? level is detected. when ix 2 is 1, ?h? level is detected. 3: when ix 2 is 0, falling edge is detected. when ix 2 is 1, rising edge is detected. (note 1) key-on wakeup input snzi1 instruction (note 1) l1 3 0 1 edge detection circuit level detection circuit p2 1 /int1 i2 3 i2 2 falling 0 1 rising l1 2 i2 1 0 1 one-sided edge detection circuit both edges detection circuit skip exf1 external 1 interrupt (note 2) (note 3) (note 1)
rev.1.02 may 25, 2007 page 22 of 124 rej03b0179-0102 4571 group (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to ?1? when a valid waveform is input to p2 0 /int0 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 22). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt contro l register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to ?0? when an interrupt occurs or when the next instruction is skipped with the skip instruction. ? external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to p2 0 /int0 pin. the valid waveform can be sele cted from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the extern al 0 interrupt is as follows. (1) set the bit 3 of register i1 to ?1? for the int0 pin to be in the input enabled state. (2) select the valid waveform with the bits 1 and 2 of register i1. (3) clear the exf0 flag to ?0? with the snz0 instruction. (4) set the nop instruction for the case when a skip is performed with the snz0 instruction. (5) set both the external 0 interrupt enable bit (v1 0 ) and the inte flag to ?1.? the external 0 interrupt is now enabled. now when a valid waveform is input to the p2 0 /int0 pin, the exf0 flag is set to ?1? and the external 0 interrupt occurs. (2) external 1 interrupt request flag (exf1) external 1 interrupt request flag (exf1) is set to ?1? when a valid waveform is input to p2 1 /int1 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 22). the state of exf1 flag can be examined with the skip instruction (snz1). use the interrupt contro l register v1 to select the interrupt or the skip instruction. the exf1 flag is cleared to ?0? when an interrupt occurs or when the next instruction is skipped with the skip instruction. ? external 1 interrupt activated condition external 1 interrupt activated condition is satisfied when a valid waveform is input to p2 1 /int1 pin. the valid waveform can be sele cted from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the extern al 1 interrupt is as follows. (1) set the bit 3 of register i2 to ?1? for the int1 pin to be in the input enabled state. (2) select the valid waveform with the bits 1 and 2 of register i2. (3) clear the exf1 flag to ?0? with the snz1 instruction. (4) set the nop instruction for the case when a skip is performed with the snz1 instruction. (5) set both the external 1 interrupt enable bit (v1 1 ) and the inte flag to ?1.? the external 1 interrupt is now enabled. now when a valid waveform is input to the p2 1 /int1 pin, the exf1 flag is set to ?1? and the external 1 interrupt occurs.
rev.1.02 may 25, 2007 page 23 of 124 rej03b0179-0102 4571 group (3) external interrupt control registers (1) interrupt control register i1 register i1 controls the valid waveform for the external 0 interrupt. set the contents of th is register through register a with the ti1a instruction. th e tai1 instruction can be used to transfer the contents of register i1 to register a. (2) interrupt cont rol register i2 register i2 controls the valid waveform for the external 1 interrupt. set the contents of th is register through register a with the ti2a instruction. th e tai2 instruction can be used to transfer the contents of register i2 to register a. note 1.?r? represents read enabled, and ?w? represents write enabled. note 2.when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. note 3.when the contents of i2 2 and i2 3 are changed, the external interrupt request flag exf1 may be set. table 15 external interrupt control register interrupt control register i1 at reset : 0000 2 at ram back-up : state retained r/w tai1/ti1a i1 3 int0 pin input control bit (note 2) 0 int0 pin input disabled 1 int0 pin input enabled i1 2 interrupt valid waveform for int0 pin/ return level selection bit (note 2) 0 falling waveform (?l? level of int0 pin is recognized with the snzi0 instruction)/?l? level 1 rising waveform (?h? level of int0 pin is recognized with the snzi0 instruction)/?h? level i1 1 int0 pin edge detection circuit control bit 0 one-sided edge detected 1 both edges detected i1 0 int0 pin timer 1 control enable bit 0 timer 1 disabled 1 timer 1 enabled interrupt control register i2 at reset : 0000 2 at ram back-up : state retained r/w tai2/ti2a i2 3 int1 pin input control bit (note 3) 0 int0 pin input disabled 1 int0 pin input enabled i2 2 interrupt valid waveform for int1 pin/ return level selection bit (note 3) 0 falling waveform (?l? level of int0 pin is recognized with the snzi1 instruction)/?l? level 1 rising waveform (?h? level of int0 pin is recognized with the snzi1 instruction)/?h? level i2 1 int1 pin edge detection circuit control bit 0 one-sided edge detected 1 both edges detected i2 0 not used 0 this bit has no function, but read/write is enabled. 1
rev.1.02 may 25, 2007 page 24 of 124 rej03b0179-0102 4571 group (4) notes on interrupts (1) bit 3 of register i1 when the input of the p2 0 /int0 pin is controlled with the bit 3 of register i1 in so ftware, be careful about the following notes. ? depending on the input state of the p2 0 /int0 pin, the external 0 interrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 24) and then, ch ange the bit 3 of register i1. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at l east one instruction (refer to (2) in figure 24). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 24). fig 24. external 0 interrupt program example-1 (2) bit 3 of register i1 when the bit 3 of register i1 is cleared to ?0?, the ram back-up mode is selected and the input of int0 pin is disabled, be careful a bout the following notes. ? when the int0 pin input is disabled (register i1 3 = ?0?), set the key-on wakeup of int0 pin to be invalid (register l1 0 = ?0?) before system enters to the ram back-up mode. (refer to (1) in figure 25). fig 25. external 0 interrupt program example-2 (3) bit 2 of register i1 when the interrupt valid waveform of the p2 0 /int0 pin is changed with the bit 2 of regist er i1 in software, be careful about the following notes. ? depending on the input state of the p2 0 /int0 pin, the external 1 interrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 26) and then, change the bit 2 of register i1 is changed. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at l east one instruction (refer to (2) in figure 26). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 26). fig 26. external 0 interrupt program example-3 ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ...... (1) la 8 ; (1 2 ) ti1a ; control of int0 pin input is changed nop ...................................................... (2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop ...................................................... (3) ? ? ? : these bits are not used here. ? ? ? la 0 ; ( 0 2 ) tl1a ; int0 key-on wakeup disabled .....(1) di epof pof ; ram back-up ? ? ? : these bits are not used here. ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ......(1) la 12 ; (1 2 ) ti1a ; interrupt valid waveform is changed nop .......................................................(2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop .......................................................(3) ? ? ? : these bits are not used here.
rev.1.02 may 25, 2007 page 25 of 124 rej03b0179-0102 4571 group (4) bit 3 of register i2 when the input of the p2 1 /int1 pin is controlled with the bit 3 of register i2 in so ftware, be careful about the following notes. ? depending on the input state of the p2 1 /int1 pin, the external 1 interrupt request flag (exf1) may be set when the bit 3 of register i2 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to ?0? (refer to (1) in figure 27) and then, ch ange the bit 3 of register i2. in addition, execute the snz1 instruction to clear the exf1 flag to ?0? after executing at l east one instruction (refer to (2) in figure 27). also, set the nop instruction for the case when a skip is performed with the snz1 instru ction (refer to (3) in figure 27). fig 27. external 1 interrupt program example-1 (5) bit 3 of register i2 when the bit 3 of register i2 is cleared to ?0?, the ram back-up mode is selected and the input of int1 pin is disabled, be careful a bout the following notes. ? when the int1 pin input is disabled (register i2 3 = ?0?), set the key-on wakeup of int1 pin to be invalid (register l2 0 = ?0?) before system enters to the ram back-up mode. (refer to (1) in figure 28) . fig 28. external 1 interrupt program example-2 (6) bit 2 of register i2 when the interrupt valid waveform of the p2 1 /int1 pin is changed with the bit 2 of regist er i2 in software, be careful about the following notes. ? depending on the input state of the p2 1 /int1 pin, the external 1 interrupt request flag (exf1) may be set when the bit 2 of register i2 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to ?0? (refer to (1) in figure 29) and then, change the bit 2 of register i2 is changed. in addition, execute the snz1 instruction to clear the exf1 flag to ?0? after executing at l east one instruction (refer to (2) in figure 29). also, set the nop instruction for the case when a skip is performed with the snz1 instru ction (refer to (3) in figure 29). fig 29. external 1 interrupt program example-3 ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz1 instruction is valid ...... (1) la 8 ; (1 2 ) ti1a ; control of int1 pin input is changed nop ...................................................... (2) snz0 ; the snz1 instruction is executed (exf1 flag cleared) nop ...................................................... (3) ? ? ? : these bits are not used here. ? ? ? la 0 ; ( 0 2 ) tl1a ; int1 key-on wakeup disabled .....(1) di epof pof ; ram back-up ? ? ? : these bits are not used here. ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz1 instruction is valid ......(1) la 12 ; (1 2 ) ti1a ; interrupt valid waveform is changed nop .......................................................(2) snz0 ; the snz1 instruction is executed (exf1 flag cleared) nop .......................................................(3) ? ? ? : these bits are not used here.
rev.1.02 may 25, 2007 page 26 of 124 rej03b0179-0102 4571 group timers the 4571 group has the following timers. ? programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be se t. it is decremented from a setting value n. when it underflows (count to n + 1), a timer interrupt request flag is set to ?1,? new data is loaded from the reload register, and count cont inues (auto-reload function). ? fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency dividing ratio (n). an interrupt request flag is set to ?1? after every n count of a count pulse. fig 30. auto-reload function n+1 count reload n+1 count an interrupt occurs or a skip instruction is executed. 1st underflow reload 2nd underflow ff 16 time n 00 16 ?1? ?0? n : counter initial value the contents of counter timer interrupt request flag count starts
rev.1.02 may 25, 2007 page 27 of 124 rej03b0179-0102 4571 group the 4571 group timer consists of the following circuits. ? prescaler : 8-bit programmable timer ? timer 1 : 8-bit programmable timer ? timer 2 : 8-bit programmable timer ? timer 3 : 8-bit programmable timer ? watchdog timer: 16-bit fixed frequency timer (timers 1, 2 and 3 have the in terrupt function, respectively) prescaler, timer 1, timer 2 and timer 3 can be controlled with the timer control registers pa, w1, w2, w3 and w5. the watchdog timer is a free counter which is not controlled with the control register. each function is described below. table 16 function related timers circuit structure count source frequency dividing ratio use of output signal control register prescaler 8-bit programmable binary down counter ? instruction clock (instck) ? instruction clock divided by 4 (instck/4) 1 to 256 ? timer 1 count source ? timer 2 count source ? timer 3 count source pa timer 1 8-bit programmable binary down counter (link to int0 input) (carrier wave output auto- control function) ? pwm signal (pwmout) ? prescaler output (orclk) ? cntr0 input (cntr0in) ? system clock (stck) 1 to 256 ? timer 2 count source ? cntr0 output ? carrier wave output auto- control ? timer 1 interrupt w1 w5 timer 2 8-bit programmable binary down counter ? pwm signal (pwmout) ? timer 1 underflow (t1udf) ? prescaler output (orclk) ? system clock (stck) 1 to 256 ? cntr0 output ? timer 2 interrupt w2 w5 timer 3 8-bit programmable binary down counter (with carrier wave generation function) ?x in input ? prescaler output divided by 2 (orclk/2) 1 to 256 ? timer 1 count source ? timer 2 count source ? cntr1 output ? timer 3 interrupt w1 w3 w5 watchdog timer 16-bit fixed dividing frequency ? instruction clock (instck) 65536 ? system reset (counting twice) ? decision of flag wdf1 -
rev.1.02 may 25, 2007 page 28 of 124 rej03b0179-0102 4571 group fig 31. timers structure (1) data is set automatically from each reload register when timer underflows (auto-reload function). x in orclk w5 0 0 1 d 4 /cntr0 1/2 port d 4 output w5 2 0 1 w2 3 0 1 t1udf t2udf p2 0 /int0 i1 2 0 1 i1 1 0 1 one-sided edge detection circuit intsnc i1 3 11 10 01 00 w2 1 ,w2 0 pwmout orclk t1udf w2 2 timer 2 (8) reload register r2 (8) register b (tab2) (t2ab) register a (t2ab) (t2ab) (tab2) t2f timer 2 interrupt t2udf stck 11 10 01 00 w1 1 ,w1 0 pwmout orclk cntr0in w1 2 w5 3 0 1 (note 1) s r q int0snc i1 0 w1 3 t1udf timer 1 (8) reload register r1 (8) register b (tab1) (t1ab) register a (t1ab) (t1ab) (tab1) t1f timer 1 interrupt t1udf stck pa 1 1 0 00 01 10 11 mr3,mr2 division circuit divided by 8 divided by 4 divided by 2 internal clock generating circuit (divided by 3) system clock (stck) instruction clock (instck) prescaler (8) pa 0 reload register rps (8) register b (tabps) (tpsab) register a (tpsab) (tpsab) (tabps) 1/4 pwmout: pwm signal (output from timer 3) cntr0in (tr1ab) both edges detection circuit note 1: timer 1 count start synchronous circ uit is synchronized with the valid edge of int pin selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1.
rev.1.02 may 25, 2007 page 29 of 124 rej03b0179-0102 4571 group fig 32. timers structure (2) watchdog reset signal reset signal (note 3) d t q r dwdt instruction + wrst instruction reset signal (note 4) (note 2) wrst instruction watchdog timer (16) 1 - - - - - - - - - - - - - 16 instck s r q wdf1 s r q wef c/cntr 1 port c output pwmout pwmod w1 2 w5 1 q r d t t1udf w3 0 0 1 x in w3 1 timer 3 (8) reload register r3l (8) register b (tab3) (t3ab) register a (t3ab) (t3ab) (tab3) (t3r3l) reload control circuit (note 1) reload register r3h (8) (t3hab) register b register a w3 3 timer 3 interrupt 1/2 orclk tq r w3 2 1 0 ?h? interval expansion t3f pwmod t2udf: timer 2 underflow signal orclk: prescaler output note 1: when the cntr1 out put function is valid (w3 3 =?1?), the value is auto-reloaded alternately from reload register r3l and r3h every timer 3 underflow. when the cntr1 function is invalid (w3 3 =?0?), the value is auto-reloaded from reload register r3l only. 2: flag wdf1 is cleared to ?0? and the next instruction is skipped when the wrst instruction is executed while flag wdf1 = ?1?. the wrst instruction is equivalent to the nop instruction while flag wdf1 = ?0?. 3: flag wef is cleared to ?0? and watchdog timer reset does not occur when the dwdt instruction and wrst instruction are executed continuously. 4: the wef flag is set to ?1? at system reset or ram back-up mode. data is set automatically from each reload register when timer underflows (auto-reload function).
rev.1.02 may 25, 2007 page 30 of 124 rej03b0179-0102 4571 group note 1. ? r ? represents read enabled, and ? w ? represents write enabled. note 2.this function is valid only when the int0 pin/timer 1 control is enabled (i1 0 = ? 1 ? ) and the timer 1 count start synchronous circuit is selected (w5 3 = ? 1 ? ). note 3.this function is valid only when t he int0 pin/timer 1 control is enabled (i1 0 = ? 1 ? ). table 17 timer control registers timer control register pa at reset : 00 2 at ram back-up : 00 2 w tpaa pa 1 prescaler count source selection bit 0 instruction clock (instck) 1 instruction clock divided by 4 (instck/4) pa 0 prescaler control bit 0 stop (state initialized) 1operating timer control register w1 at reset : 0000 2 at ram back-up : state retained r/w taw1/tw1a w1 3 timer 1 count auto-stop circuit selection bit (note 2) 0 timer 1 count auto-stop circuit not selected 1 timer 1 count auto-stop circuit selected w1 2 timer 1 control bit 0 stop (state retained) 1operating timer 1 count source selection bits w1 1 w1 0 count source w1 1 0 0 pwm signal (pwmout) 0 1 prescaler output (orclk) 1 0 system clock (stck) w1 0 1 1 cntr0 input timer control register w2 at reset : 0000 2 at ram back-up : state retained r/w taw2/tw2a w2 3 cntr0 pin function selection bit 0 timer 1 underflow signal divided by 2 output 1 timer 2 underflow signal divided by 2 output w2 2 timer 2 control bit 0 stop (state retained) 1operating timer 2 count source selection bits w2 1 w2 0 count source w2 1 0 0 pwm signal (pwmout) 0 1 prescaler output (orclk) 1 0 system clock (stck) w2 0 1 1 timer 1 underflow signal (t1udf) timer control register w3 at reset : 0000 2 at ram back-up : 0000 2 r/w taw3/tw3a w3 3 cntr1 pin output control bit 0 cntr1 pin output invalid 1 cntr1 pin output valid w3 2 pwm signal ? h ? interval expansion function control bit 0 pwm signal ? h ? interval expansion function invalid 1 pwm signal ? h ? interval expansion function valid w3 1 timer 3 control bit 0 stop (state retained) 1operating w3 0 timer 3 count source selection bit 0x in input 1 prescaler output (orclk)/2 timer control register w5 at reset : 0000 2 at ram back-up : state retained r/w taw5/tw5a w5 3 timer 1 count start synchronous circuit selection bit (note 3) 0 count start synchronous circuit not selected 1 count start synchronous circuit selected w5 2 cntr0 pin input count edge selection bit 0 falling edge 1 rising edge w5 1 cntr 1 pin output auto-control circuit selection bit 0 output auto-control circuit not selected 1 output auto-control circuit selected w5 0 d 4 /cntr0 pin function selection bit 0d 4 (i/o) / cntr0 (input) 1d 4 (input) /cntr0 (i/o)
rev.1.02 may 25, 2007 page 31 of 124 rej03b0179-0102 4571 group (1) timer control registers ? timer control register pa register pa controls the count operation and count source of prescaler. set the contents of this register through register a with the tpaa instruction. ? timer control register w1 register w1 controls the coun t operation and count source of timer 1, and timer 1 count auto-s top circuit. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. ? timer control register w2 register w2 controls the coun t operation and count source of timer 2, and cntr0 pin out put signal function. set the contents of this register th rough register a with the tw2a instruction. the taw2 instruction can be used to transfer the contents of register w2 to register a. ? timer control register w3 register w3 controls timer 3 count source, timer 3 count operation, cntr1 pin output and pwm signal ?h? interval expansion function. set the conten ts of this register through register a with the tw3a instruction. the taw3 instruction can be used to transfer the cont ents of register w3 to register a. ? timer control register w5 register w5 controls the input count edge of cntr0 pin, the timer 1 count start synchrono us circuit, cntr1 pin output auto-control circuit and the d 4 /cntr1 pin function. set the contents of this register th rough register a with the tw5a instruction. the taw5 instruction can be used to transfer the contents of register w5 to register a. (2) prescaler prescaler is an 8-bit binary down counter with the prescaler reload register rps. data can be set simultaneously in prescaler and the reload register rps with the tpsab instruction. data can be read from reload register rps with the tabps instruction. stop counting and then execute the tpsab or tabps instruction to read or set prescaler data. prescaler starts counting after the following process; (1) set data in prescaler, and (2) set the bit 0 of register pa to ?1.? when a value set in reload register rps is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). count source for prescaler can be selected the instruction clock (instck) or the instru ction clock (instck)/4. once count is started, when pr escaler underflows (the next count pulse is input after the contents of prescaler becomes ?0?), new data is loaded from reload regi ster rps, and count continues (auto-reload function). the output signal (orclk) of pres caler can be used for timer 1 and 2 count sources. (3) timer 1 (inte rrupt function) timer 1 is an 8-bit binary down counter with a timer 1 reload register (r1). data can be set simultaneously in timer 1 and the reload register r1 with the tr1a b instruction. data can be read from timer 1 with the tab1 instruction. stop counting and then execute the t1ab or tab1 instruction to read or set timer 1 data. when executing the tr1ab instru ction to set data to reload register r1 while timer 1 is ope rating, avoid a t iming when timer 1 underflows. timer 1 starts counting af ter the following process; (1) set data in timer 1 (2) set count source by bits 0 and 1 of register w1, and (3) set the bit 2 of register w1 to ?1.? when a value set in reload register r1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes ?0?), the timer 1 interrupt request flag (t1f) is set to ?1,? new data is loaded from reload register r1, and count continues (auto-reload function). after timer 1 control by int0 pin is enabled by setting the bit 0 of register i1 to ?1?, int0 pin input can be used as the start trigger for timer 1 count operati on by setting the bit 3 of register w5 to ?1?. also, in this time, the auto-stop function by timer 1 underflow can be performed by se tting the bit 3 of register w1 to ?1.? the timer 1 underflow signal divided by 2 can be output from the cntr0 pin by setting the bit 0 of re gister w5 to ?1? and bit 3 of register w2 to ?0?. (4) timer 2 (inte rrupt function) timer 2 is an 8-bit binary dow n counter with timer 2 reload register (r2). data can be set simultaneously in timer 2 and the reload register r2 with the t2ab instruction. data can be read from timer 2 with the tab2 instruction. stop counting and then execute the t2ab or tab2 instruction to read or set timer 2 data. timer 2 starts counting af ter the following process; (1) set data in timer 2 (2) set count source by bits 0 and 1 of register w2, and (3) set the bit 2 of register w2 to ?1.? when a value set in reload register r2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes ?0?), the timer 2 interrupt request flag (t2f) is set to ?1,? new data is loaded from reload register r2, and count continues (auto-reload function). the timer 2 underflow signal divided by 2 can be output from the cntr0 pin by setting the bit 0 of re gister w5 to ?1? and bit 3 of register w2 to ?1?.
rev.1.02 may 25, 2007 page 32 of 124 rej03b0179-0102 4571 group (5) timer 3 (interrupt function) timer 3 is an 8-bit binary dow n counter with two timer 3 reload registers (r3l, r3h). data can be set simultaneously in timer 3 and the reload register r3l with the t3ab instruction. data can be set in the reload register r3h with the t3hab instruction. the contents of reload regi ster r3l set with the t3ab instruction can be set to timer 3 again with the t3r3l instruction. data can be read from timer 3 with the tab3 instruction. stop counting and then execute the t3ab or tab3 instruction to read or set timer 3 data. when executing the t3 hab instruction to set data to reload register r3h while timer 3 is operating, avoid a timing when timer 3 underflows. timer 3 starts counting af ter the following process; (1) set data in timer 3 (2) set count source by bit 0 of register w3, and (3) set the bit 1 of register w3 to ?1.? when a value set in reload register r3l is n and a value set in reload register r3h is m, timer 3 divides th e count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). once count is started, when time r 3 underflows (the next count pulse is input after the contents of timer 3 becomes ?0?), the timer 3 interrupt request flag (t3f) is set to ?1,? new data is loaded from reload register r3 l, and count continues (auto- reload function). timer 3 generates the pwm signal of the ?l? interval set as reload register r3l, and the ?h? interval set as reload register r3h. the pwm (pwmod) signal generated by timer 3 is output from cntr1 pin. when bit 2 of register w3 is set to ?1? at this time, timer 3 extends the interval set to reload register r3h for a half period of count source. when a value set in reload register r3h is n, timer 3 divides the count source signal by m + 1.5 (m = 1 to 255). when this function is used, set ?1? or more to reload register r3h. when bit 1 of register w5 is se t to ?1?, the pwm signal output to cntr1 pin is switched to valid/ invalid each timer 1 underflow. however, when timer 3 is stoppe d, this function is canceled. even when bit 1 of a register w3 is cleared to ?0? in the ?h? interval of pwm signal, timer 3 does not stop until it next timer 3 underflow. when bit 1 of register w3 is clea red to ?0? in order to stop timer 3 while the pwm output is used, avoid a timing when timer 3 underflows. if these timings overlap, a haza rd may occur in a cntr1 output waveform. (6) count start synchron ization circuit (timer 1) timer 1 has the count start synchronous circuit which synchronizes the input of int0 pi n, and can start the timer count operation. timer 1 count start synchronous circuit function can be selected after timer 1 control by int0 pin is enabled by setting the bit 0 of register i1 to ?1? and its functi on is selected by setting the bit 3 of register w5 to ?1?. when timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count sour ce is input to timer by inputting valid waveform to int0 pin. the valid waveform of int0 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. once set, the count start s ynchronous circuit is cleared by clearing the bit i1 0 to ?0? or system reset. however, when the count auto-st op circuit is selected, the count start synchronous circuit is clea red (auto-stop) at the timer 1 underflow. (7) count auto-sto p circuit (timer 1) timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. the count auto-stop circuit is valid by setting the bit 3 of register w1 to ?1?. it is cleared by the timer 1 underflow and the count source to time r 1 is stopped. this function is valid only when the timer 1 count start synchronous circuit is selected. (8) timer input/output pin (d 4 /cntr0) cntr0 pin is used to input the timer 1 count source and output the timer 1 or time r 2 underflow signal/2. the d 4 /cntr0 pin function can be se lected by bit 0 of register w5. the output signal can be selected by bit 0 of register w2. when the cntr0 input is sel ected for timer 1 count source, timer 1 counts the fa lling or rising waveform of cntr0 input. the count edge is selected by bit 2 of register w5. (9) pwm signal output f unction (c/cnt r1, timer 1, timer 2) the c/cntr1 pin is also used to output the pwm signal generated by timer 3. when the bit 3 of register w3 is set to ?1?, the pwm signal can be output from the c/cntr1 pin. in this time, set the output latch of port c to ?1.? (10)timer interrupt request flags (t1f, t2f, t3f) each timer interrupt request flag is set to ?1? when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1, snzt2, snzt3). use the interrupt control register v1, v2 to select an interrupt or a skip instruction. an interrupt request flag is cl eared to ?0? when an interrupt occurs or when the next instruction is skipped with a skip instruction.
rev.1.02 may 25, 2007 page 33 of 124 rej03b0179-0102 4571 group (11) precautions ? prescaler stop prescaler counting and then execute the tabps instruction to read its data. stop prescaler counting and then execute the tpsab instruction to write data to prescaler. stop prescaler counting to change its count source. ? timer count source stop timer 1, 2 or 3 counting to change its count source. ? reading the count value stop timer 1, 2 or 3 counting and then execute the tab1, tab2 or tab3 instruction to read its data. ? writing to the timer stop timer 1, 2 or 3 counting and then execute the t1ab, t2ab, t3ab or t3r3l instruction to write data to timer. ? writing to reload register in order to write a data to the reload register r1 while the timer 1 is operating, execute the tr1ab instruction except a timing of the timer 1 underflow. in order to write a data to the reload register r3h while the timer 3 is operating, execute th e t3hab instruction except a timing of the timer 3 underflow. ? pwm signal if the timer 3 count stop timing and the timer 3 underflow timing overlap during output of the pwm signal, a hazard may occur in the pwm output waveform. when ?h? interval expansion f unction of the pwm signal is used, set ?1? or more to reload register r3h. set the port c output latch to ?0? to output the pwm signal from c/cntr1 pin. ? prescaler, timer 1, timer 2 and timer 3 count start timing and count time when operation starts count starts from the first rising edge of the count source (2) in figure 33 after prescaler and timer operations start (1) in figure 33. time to first underflow (3) in figu re 33 is shorter (for up to 1 period of the count source) than time among next underflow (4) in figure 33 by the timing to start the timer and count source operations after count starts. when selecting cntr0 input as the count source of timer 1, timer 1 operates synchronizing with the count edge (falling edge or rising edge) of cntr 0 input selected by software. fig 33. timer count start timing and count time when operation starts count source (3) (4) (1) timer start (2) count source (when falling edge of cntr0 input is selected) timer 1 value timer 1 underflow signal 32 1 0 3 2 1 0 3 2
rev.1.02 may 25, 2007 page 34 of 124 rej03b0179-0102 4571 group fig 34. timer 3 operation example timer 3 count source timer 3 start timer 3 count value (reload register) timer 3 underflow signal pwm signal 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 (r3l) (r3l) (r3l) (r3l) (r3l) pwm1 signal ?l? fixed - cntr1 pin output invalid (w3 3 =0) timer 3 count source timer 3 start timer 3 count value (reload register) timer 3 underflow signal pwm signal 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 03 16 (r3l) (r3h) (r3l) (r3h) (r3l) (r3h) pwm period 7 clock pwm period 7 clock * : ?03 16 ? is set to reload register r3l and ?02 16 ? is set to reload register r3h. 4 clock 3 clock 4 clock 3 clock 4 clock timer 3 count source timer 3 start timer 3 count value (reload register) timer 3 underflow signal pwm signal 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 03 16 (r3l) (r3h) (r3l) (r3h) (r3l) (r3h) pwm period 7.5 clock pwm period 7.5 clock 4 clock 3.5 clock 4 clock 3.5 clock 4 clock note: when the pwm signal ?h? interval expansion function is valid, set ?1? or more to reload register r3h. - cntr1 pin output valid (w3 3 =1), pwm signal ?h? interval expansion function invalid (w3 2 =0) - cntr1 pin output valid (w3 3 =1), pwm signal ?h? interval expansion function valid (w3 2 =1) (note)
rev.1.02 may 25, 2007 page 35 of 124 rej03b0179-0102 4571 group fig 35. cntr1 output auto-control function by timer 1 timer 1 start cntr1 output start timer 1 underflow signal pwm signal ? cntr1 output auto-control circuit operation example 1 (w3 3 = ?1?, w5 1 = ?1?) cntr1 output * when the cntr1 output auto-control circuit is selected, valid/invalid of cntr1 output is repeated every timer 1 underflows. ? cntr1 output auto-control circuit operation example 2 (w3 3 = ?1?, w5 1 = ?1?) timer 1 start cntr1 output start timer 1 underflow signal pwm signal register w5 1 timer 1 stop cntr1 output stop cntr1 output (1) when the cntr1 output auto-control function is not selected while the cntr1 output is invalid, cntr1 output invalid state is retained. (2) when the cntr1 output auto-control function is not selected while the cntr1 output is valid, cntr1 output valid state is retained. (3) when the timer 1 is stopped, the cntr1 output auto-control function becomes invalid. (1) (2) (3)
rev.1.02 may 25, 2007 page 36 of 124 rej03b0179-0102 4571 group fig 36. timer count start/stop timing (r3h) timer 3 underflow signal machine cycle timer 3 count start timing (r3l = ?02 16 ?, r3h = ?02 16 ?, w3 3 = ?1?) register w3 1 mi mi + 1 mi + 2 mi + 3 02 16 00 16 01 16 02 16 00 16 01 16 02 16 (r3l) (r3l) timer 3 count start timing pwm signal timer 3 count value (reload register) timer 3 count source (x in input) (r3h) mi mi + 1 mi + 2 mi + 3 00 16 01 16 02 16 00 16 01 16 02 16 02 16 timer 3 count stop timing (r3l) (r3h) (note 1) tw3a instruction execution (w3 1 1) tw3a instruction execution (w3 1 0) timer 3 underflow signal machine cycle register w3 1 pwm signal timer 3 count value (reload register) timer 3 count source (x in input) timer 3 count stop timing (r3l = ?02 16 ?, r3h = ?02 16 ?, w3 3 = ?1?) notes 1: if the timer count stop timing and the timer underflow timing overlap while the cntr1 pin output is valid (w3 3 =?1?), a hazard may occur in the pwm signal waveform. 2: when timer count is stopped during ?h? interval of the pwm signal, timer is stopped after the end of the ?h? output interval.
rev.1.02 may 25, 2007 page 37 of 124 rej03b0179-0102 4571 group watchdog timer watchdog timer provides a method to reset the system when a program run-away occurs. watchdog timer consists of timer wdt(16-bit binary counter), wa tchdog timer enable flag (wef), and watchdog timer flags (wdf1, wdf2). the timer wdt downcounts the inst ruction clocks as the count source from ?ffff 16 ? after system is released from reset. after the count is started, wh en the timer wdt underflow occurs (after the count value of timer wdt reaches ?0000 16 ,? the next count pulse is input), the wdf1 flag is set to ?1.? if the wrst instruction is never executed until the timer wdt underflow occurs (until timer wdt counts 65 534), wdf2 flag is set to ?1,? and the reset pin outputs ?l? level to reset the microcomputer. execute the wrst instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. when the wef flag is set to ?1? after system is released from reset, the watchdog time r function is valid. when the dwdt instruction a nd the wrst instruction are executed continuously, the wef fl ag is cleared to ?0? and the watchdog timer func tion is invalid. the wef flag is initialized to ?1? at system reset or ram back- up mode. the wrst instruction has the skip function. when the wrst instruction is executed while the wdf1 flag is ?1?, the wdf1 flag is cleared to ?0? and th e next instruction is skipped. when the wrst instruction is executed while the wdf1 flag is ?0?, the next instruction is not skipped. the skip function of the wrst instruction can be used even when the watchdog timer function is invalid. fig 37. watchdog timer function (1) reset released 65534 count (note) (4) (2) (2) (3) wrst instruction executed (skip executed) (5) system reset ffff 16 0000 16 value of 16-bit timer (wdt) wdf1 flag wdf2 flag reset pin output (1) after system is released from reset (= after program is started), time r wdt starts count down. (2) when timer wdt underflow occu rs, wdf1 flag is set to ?1?. (3) when the wrst instruction is executed while the wdf1 flag is ?1?, wdf1 flag is cleared to ?0?, the next instruction is skipped. (4) when timer wdt underflow occurs while wdf1 flag is ?1?, wdf2 flag is set to ?1? and the watchdog reset signal is output. (5) the output transistor of reset pin is turned ?o n? by the watchdog reset signal and system reset is executed. note: the number of count is equal to the number of ma chine cycle because the count source of watchdog timer is the instruction clock.
rev.1.02 may 25, 2007 page 38 of 124 rej03b0179-0102 4571 group when the watchdog timer is used, clear the wdf1 flag at the period of 65534 machine cycles or less with the wrst instruction. when the watchdog timer is not used, execute the dwdt instruction and the wrst instruction continuously (refer to figure 38). the watchdog timer is not stopped with only the dwdt instruction. the contents of wdf1 flag and timer wdt are initialized at the ram back-up mode. when using the watchdog timer and the ram back-up mode, initialize the wdf1 flag with th e wrst instruction just before the microcomputer enters the ra m back-up state. also, set the nop instruction after the wrst instruction, for the case when a skip is performed with the wrst instruction (refer to figure 39). fig 38. program example to start/stop watchdog timer fig 39. program example when using the watchdog timer ? ? ? wrst ; wdf1 flag cleared ? ? ? di dwdt ; watchdog timer fu nction enabled/disabled wrst ; wef and wdf1 flags cleared ? ? ? ? ? ? wrst ; wdf1 flag cleared nop di ; interrupt disabled epof ; pof instruction enabled pof ; ram back-up mode oscillation stop ? ? ?
rev.1.02 may 25, 2007 page 39 of 124 rej03b0179-0102 4571 group reset function system reset is performed by the followings: ? ?l? level is applied to the reset pin externally, ? system reset instruction (srst) is executed, ? reset occurs by watchdog timer, ? reset occurs by built-in power-on reset ? reset occurs by voltage drop detection circuit then when ?h? level is applied to reset pin, software starts from address 0 in page 0. (1) reset pin input system reset is performed ce rtainly by applying ?l? level to reset pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended opera ting conditions. fig 40. structure of reset pin and its peripherals fig 41. reset pin input waveform and reset release timing power-on reset circuit watchdog reset signal wef srst instruction internal reset signal (note 1) reset pin (note 2) pull-up transistor voltage drop detection circuit (note 1) notes 1: this symbol represents a parasitic diode. 2: applied potential to reset pin must be v dd or less. 0.3v dd 0.85v dd (note 1) program starts (address 0 in page 0) reset input 1 machine cycle or more reset f(ring) notes 1: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 2: it depends on the internal state at reset. x in input is counted 5400 to 5424 times (note 2). =
rev.1.02 may 25, 2007 page 40 of 124 rej03b0179-0102 4571 group (2) power-on reset reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 v to the minimum voltage of recommended operating conditions to 100 s or less. if the rising time exceeds 100 s, connect a capacitor between the reset pin and vss at the shortest distance, and input ?l? level to reset pin until the value of supply voltage reaches the minimum operating voltage. (3) system reset instruction (srst) by executing the srst instructi on, ?l? level is output to reset pin and system reset is performed. fig 42. power-on reset operation note 1.output latch is set to ?1.? note 2.the output structure is n-channel open-drain. note 3.pull-up transistor is turned off. 100 sor less v dd (note 1) power-on reset circuit output internal reset signal note: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. reset released reset state power-on table 18 port state at reset name function state d 0 ? d 3 d 0 ? d 3 high-impedance (notes 1, 2) d 4 /cntr0 d 4 high-impedance (note 1) p0 0 ? p0 3 p0 0 ? p0 3 high-impedance (notes 1, 3) p1 0 ? p1 3 p1 0 ? p1 3 high-impedance (notes 1, 3) p2 0 /int0, p2 1 /int1 p2 0 , p2 1 high-impedance (notes 1, 3) p3 0, p3 1 p3 0, p3 1 high-impedance (notes 1, 2) c/cntr1 c/cntr1 (v ss ) k k high-impedance
rev.1.02 may 25, 2007 page 41 of 124 rej03b0179-0102 4571 group (4) internal state at reset figure 43 shows internal state at reset (they are the same after system is released from reset). the contents of timers, registers, flags and ram except shown in figu re 43 are undefined, so set the initial value to them. fig 43. internal state at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? program counter (pc) address 0 in page 0 is set to program counter. ? interrupt enable flag (inte) ? power down flag (p) ? external 0 interrupt request flag (exf0) ? external 1 interrupt request flag (exf1) ? interrupt control register v1 ? interrupt control register v2 ? interrupt control register i1 ? interrupt control register i2 ? timer 1 interrupt request flag (t1f) ? timer 2 interrupt request flag (t2f) ? timer 3 interrupt request flag (t3f) ? watchdog timer flags (wdf1, wdf2) ? watchdog timer enable flag (wef) ? timer control register pa ? timer control register w1 ? timer control register w2 ?timer control register w3 ? timer control register w5 ? clock control register mr 0 (interrupt disabled) 0 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0 0 0 0 0 0 0 0 0 0 1 0 (prescaler stopped) 0 (timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 ? key-on wakeup control register k0 ? key-on wakeup control register k1 ? key-on wakeup control register k2 ? key-on wakeup control register l1 ? pull-up control register pu0 ? pull-up control register pu1 ? pull-up control register pu2 ? port output structure control register fr0 ? port output structure control register fr1 ? carry flag (cy) ? register a ? register b ? register d ? register e ? register x ? register y ? register z ? stack pointer (sp) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 ?x? represents undefined. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (timer 3 stopped) 0
rev.1.02 may 25, 2007 page 42 of 124 rej03b0179-0102 4571 group voltage drop detection circuit the built-in voltage drop detectio n circuit is used to set the voltage drop detection circuit inte rrupt request flag (vdf) or to perform system reset. the voltage drop detection circu it stops at ram back-up mode. fig 44. voltage drop detection reset circuit wef v rst - /v rst + - + v int - + interrupt occurrence reset occurrence vdf voltage drop detection circuit interrupt s r q q oscillation stop signal key-on wakeup signal epof instruction + pof instruction power-on reset circuit watchdog reset signal srst instruction internal reset signal (note 1) reset pin (note 2) pull-up transistor voltage drop detection circuit (note 1) notes 1: this symbol represents a parasitic diode. 2: applied potential to reset pin must be v dd or less.
rev.1.02 may 25, 2007 page 43 of 124 rej03b0179-0102 4571 group (1) voltage drop detection ci rcuit interrup t request flag (vdf) voltage drop detection circuit inte rrupt request flag (vdf) is set to ?1? when the supply voltage goes the defined value (v int ) or less. moreover, voltage drop dete ction circuit interrupt request flag (vdf) is cleared to ?0? wh en the supply voltage goes the defined value (v int ) or more. the state of the interrupt request flag can be examined with the skip instruction (snzvd). use the interrupt control register v2 to select an interrupt or a skip instruction. unlike other interrupt request flags, even when the interrupt occurs or the skip in struction is executed, the voltage drop detection circuit interrupt reque st flag is not cleared to ?0?. (2) voltage drop detection circuit reset system reset is performed when the supply voltage goes the defined value (v rst - ) or less (?l? level is not output to reset pin.). however, unlike the normal system reset, the oscillation circuit is stopped. when the supply voltage goes the defined value (v rst - ) or more, the oscillation circuit goes to be in the operating enabled state and system reset is released. fig 45. voltage drop detection circuit operation waveform fig 46. v dd and v rst - (3) note on voltage drop detection circuit the voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recommende d operating conditions. when the supply voltage of a mic rocomputer falls below to the minimum value of recommended operating conditions and rises again, depending on the capacity value of the bypass capacitor added to the power supply pi n, the following case may cause program failure (figure 46); supply voltage does not fall below to v rst - , and its voltage rises ag ain with no reset. in such a case, please design a system which supply voltage is once reduced below to v rst - and re-goes up after that. v dd voltage drop detection circuit interrupt request flag (vdf) v rst + (reset release voltage) v rst - (reset occurrence voltage) voltage drop detection circuit reset signal notes 1: microcomputer starts operation after input clock is counted 5400 to 5424 times. 2: ?l? level is not output from reset pin. the oscillation circuit is stopped. 3: after microcomputer starts operation, the detection of the interrupt occurrence voltage is performed. (note 1) (note 2) (note 3) v int (interrupt occurrence voltage ) v dd v rst + v rst - v dd v rst + v rst - recommended operating condition min.value normal operation reset no reset program failure may occur. recommended operating condition min.value
rev.1.02 may 25, 2007 page 44 of 124 rej03b0179-0102 4571 group ram back-up mode the 4571 group has the ram back-up mode. when the pof instruction is executed continuously after the epof instruction, system en ters the ram back-up state. the pof instruction is equal to the nop instruction when the epof instruction is not execut ed before the pof instruction. as oscillation stops retaining ram, the function of reset circuit and states at ram back-up mode, current dissipation can be reduced without losing the contents of ram. table 19 shows the function and st ates retained at ram back-up. figure 47 shows the state transition. (1) identification of the start condition warm start (return from the ram back-up state) or cold start (return from the normal rese t state) can be identified by examining the state of the power down flag (p) with the snzp instruction. (2) warm start condition when the external wakeup signal is input after the system enters the ram back-up state by executing the epof instruction and pof instruction continuously, the cpu starts executing the program from address 0 in page 0. in this case, the p flag is ?1.? (3) cold start condition the cpu starts executing the progr am from address 0 in page 0 when; ? ?l? level is applied to reset pin, ? system reset (srst) is performed, ? reset by watchdog ti mer is performed, ? reset by the built-in power-on reset circuit is performed, or ? reset by the voltage drop dete ction circuit is performed. in this case, the p flag is ?0.? note 1.?o? represents that the function can be retained, and ? ? represents that the function is initialized. registers and flags other than the above are undefined at ram back-up, and set an initial value after returning. note 2.the stack pointer (sp) points the level of the stack register and is initialized to ?7? at ram back-up. note 3.the state of the timer is undefined. note 4.initialize the watchdog timer flag wdf1 with the wrst instruction, and then set the system to be in the ram back-up mode. note 5.the voltage drop detection circuit is invalid. note 6.c/cntr pin outputs ?l? level. other ports retain their output levels. table 19 functions and states retained at ram back-up function ram back-up program counter (pc), stack pointer (sp) (table 2), carry flag (cy), registers a, b contents of ram o interrupt control registers v1, v2 interrupt control registers i1, i2 o clock control register mr timer 1, timer 2, timer 3 function (note 3) watchdog timer function (note 4) timer control registers pa, w3 timer control registers w1, w2, w5 o voltage drop detection circuit (note 5) port level (note 6) key-on wakeup control registers k0 to k2, l1 o pull-up control registers pu0 to pu2 o port output structure control registers fr0, fr1 o external interrupt request flags (exf0, exf1) timer interrupt request flags (t1f, t2f, t3f) (note 3) voltage drop detection circ uit interrupt request flag (vdf) interrupt enable flag (inte) watchdog timer flags (wdf1, wdf2) (note 4) watchdog timer enable flag (wef) (note 4)
rev.1.02 may 25, 2007 page 45 of 124 rej03b0179-0102 4571 group (4) return signal an external wakeup signal is used to return from the ram back- up mode because the oscillation is stopped. table 20 shows the return condition for ea ch return source. (5) control registers ? key-on wakeup control register k0 register k0 controls the port p0 key-on wakeup function. set the contents of this register through register a with the tk0a instruction. in addition, the t ak0 instruction can be used to transfer the contents of register k0 to register a. ? key-on wakeup control register k1 register k1 controls the port p1 key-on wakeup function. set the contents of this register through register a with the tk1a instruction. in addition, the t ak1 instruction can be used to transfer the contents of register k1 to register a. ? key-on wakeup control register k2 register k2 controls the ports k and p2 key-on wakeup function. set the contents of th is register through register a with the tk2a instruction. in addition, the tak2 instruction can be used to transfer the conten ts of register k2 to register a. ? key-on wakeup cont rol register l1 register l1 controls the select ion of the selection of the int0 pin return condition and int0 pin key-on wakeup function and the selection of the int1 pin return condition and int1 pin key-on wakeup function. set the contents of this register through register a with the tl1a instruction. in addition, the tal1 instruction can be used to transfer the contents of register l1 to register a. ? pull-up control register pu0 register pu0 controls the on/off of the port p0 pull-up transistor. set the contents of th is register through register a with the tpu0a instruction. in addition, the tapu0 instruction can be used to transfer the contents of register pu0 to register a. ? pull-up control register pu1 register pu1 controls the on/off of the port p1 pull-up transistor. set the contents of th is register through register a with the tpu1a instruction. in addition, the tapu1 instruction can be used to transfer the contents of register pu1 to register a. ? pull-up control register pu2 register pu2 controls the on/ off of the ports p2 pull-up transistor. set the contents of th is register through register a with the tpu2a instruction. in addition, the tapu2 instruction can be used to transfer the contents of register pu2 to register a. ? interrupt control register i1 register i1 controls the valid waveform/level of the int0 pin and the input control of int0 pin. set the contents of this register through register a wi th the ti1a instruction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. table 20 return source and return condition return source return condition remarks external wakeup signal port p0 0 ? p0 3 port p1 0 ? p1 3 port p2 0 , p2 1 port k return by an external falling edge (?h? ?l?) input. the key-on wakeup function can be selected by one port unit. set the port using the key-on wakeup function to ?h? level before going into the ram back-up state. int pin return by an external ?h? level or ?l? level input, or falling edge (?h? ?l?) or rising edge (?l? ?h?). when the return level is input, the exf0 flag is not set. the key-on wakeup function can be selected by one port unit. select the return level (?l? level or ?h? level) with the register i1 and return condition (level or edge) with the register l1 according to the external state before going into the ram back-up state.
rev.1.02 may 25, 2007 page 46 of 124 rej03b0179-0102 4571 group fig 47. state transition fig 48. set source and clear source of the p flag fig 49. start condition identified example using the snzp instruction notes 1: microcomputer starts its operation after counting f( x in ) 5400 to 5424 times from system is released from reset. 2: continuous execution of the epof instruction and the pof instruction is required to go into the ram back-up state. 3: the operation mode also returns to the initial state (internal frequency divided by 4 mode) (register mr initialized). state a operating state f(x in ) : operating pof instruction execution (note 2) key-on wakeup (notes 1, 3) reset (note 1) state d ram back-up mode f(x in ) : stop q s + r epof instruction pof instruction internal reset signal power down flag (p) - set source ... - clear source ... reset epof instruction + pof instruction p = ?1? ? yes no warm start snzp instruction cold start software start
rev.1.02 may 25, 2007 page 47 of 124 rej03b0179-0102 4571 group note 1.?r? represents read enabled, and ?w? represents write enabled. table 21 key-on wakeup control registers key-on wakeup control register k0 at reset : 0000 2 at ram back-up : state retained r/w tak0/tk0a k0 3 port p0 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 2 port p0 2 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 1 port p0 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 0 port p0 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k1 at reset : 0000 2 at ram back-up : state retained r/w tak1/tk1a k1 3 port p1 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 2 port p1 2 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 1 port p1 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 0 port p1 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k2 at reset : 0000 2 at ram back-up : state retained r/w tak2/tk2a k2 3 not used 0 this bit has no function, but read/write is enabled. 1 k2 2 port k key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k2 1 port p2 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k2 0 port p2 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register l1 at reset : 0000 2 at ram back-up : state retained r/w tal1/tl1a l1 3 int1 pin return condition selection bit 0 return by level 1 return by edge l1 2 int1 pin valid waveform/ level selection bit 0 key-on wakeup not used 1 key-on wakeup used l1 1 int0 pin return condition selection bit 0 return by level 1 return by edge l1 0 int0 pin key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used
rev.1.02 may 25, 2007 page 48 of 124 rej03b0179-0102 4571 group note 1.?r? represents read enabled, and ?w? represents write enabled. table 22 pull-up control registers pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained r/w tapu0/tpu0a pu0 3 port p0 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 2 port p0 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 1 port p0 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 0 port p0 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained r/w tapu1/tpu1a pu1 3 port p1 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 2 port p1 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 1 port p1 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 0 port p1 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained r/w tapu2/tpu2a pu2 3 not used 0 this bit has no function, but read/write is enabled. 1 pu2 2 not used 0 this bit has no function, but read/write is enabled. 1 pu2 1 port p2 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 0 port p2 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on
rev.1.02 may 25, 2007 page 49 of 124 rej03b0179-0102 4571 group clock control the clock control circuit consis ts of the foll owing circuits. ? ceramic oscill ation circuit ? frequency divider ? internal clock generating circuit the system clock and the instruct ion clock are generated as the source clock for opera tion by these circuits. figure 50 shows the structure of the clock control circuit. fig 50. clock control circuit structure x in 00 01 10 11 mr 3 , mr 2 division circuit divided by 8 divided by 4 divided by 2 internal clock generation circuit (divided by 3) system clock (stck) instruction clock (instck) ceramic oscillation circuit voltage drop detection circuit (reset occurs) s r q epof instruction + pof instruction key-on wakeup signal reset oscillation stop signal
rev.1.02 may 25, 2007 page 50 of 124 rej03b0179-0102 4571 group (1) ceramic resonator when the ceramic resonator is used as the main clock (f(x in )), connect the ceramic res onator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in between pins x in and x out (figure 51). (2) external clock when the external signal cloc k is used for the main clock (f(x in )), connect the x in pin to the clock source and leave x out pin open (figure 52). be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). also, note that the ram back-u p mode (pof instruction) cannot be used when using the external clock. (3) clock control register mr register mr controls the select ion of operation mode. set the contents of this register th rough register a with the tmra instruction. in addition, the ta mr instruction can be used to transfer the contents of register mr to register a. fig 51. ceramic resonator external circuit fig 52. external clock input circuit note 1.?r? represents read enabled, and ?w? represents write enabled. x in x out c in c out rd note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manufacturer?s recommended value because constants such as capacitance depend on the resonator . 4571 x in x out 4571 external oscillation circuit v dd v ss table 23 return source and return condition clock control register mr at reset : 1111 2 at ram back-up : 1111 2 r/w tamr/tmra mr 3 operation mode selection bits mr 3 mr 2 operation mode 0 0 through mode (frequency not divided) 0 1 frequency divided by 2 mode mr 2 1 0 frequency divided by 4 mode 1 1 frequency divided by 8 mode mr 1 not used 0 this bit has no function, but read/write is enabled. 1 mr 0 not used 0 this bit has no function, but read/write is enabled. 1
rev.1.02 may 25, 2007 page 51 of 124 rej03b0179-0102 4571 group qzrom writing mode in the qzrom writing mode , the user rom area can be rewritten while the microcomputer is mounted on-board by using a serial pro-grammer which is a pplicable for this microcomputer. table 24 lists the pin descript ion (qzrom writing mode) and figure 53 shows the pin connections. refer to figure 54 for examples of a connection with a serial pro- grammer. contact the manufacturer of y our serial programmer for serial pro-grammer. refer to the user?s manual of your serial programmer for details on how to use it. table 24 pin description (qzrom writing mode) pin name i/o function v dd power source ? ? power supply voltage pin. v ss gnd ? ? gnd pin. kv pp input ? ? qzrom programmable power source pin. p0 1 sda input/output i/o ? qzrom serial data i/o pin. p0 0 sclk input input ? qzrom serial clock input pin. p1 0 pgm input input ? qzrom read/program pulse input pin. reset reset input input ? reset input pin. ? input ?l? level signal. x in clock input ? ? either connect an oscillat ion circuit or connect x in pin to v ss and leave the x out pin open. x out clock output ? p0 2 , p0 3 , p1 1 ? p1 3 , p2 0 /int0, p2 1 /int1, p3 0 , p3 1 , d 0 ? d 3 , d4/cntr0, c/cntr1 i/o port i/o ? input ?h? or ?l? le vel signal or leave the pin open.
rev.1.02 may 25, 2007 page 52 of 124 rej03b0179-0102 4571 group fig 53. pin connection diagram package code: prsp00 24ga-a (24p2q-a) 12 p1 1 p1 2 11 p1 0 p1 3 10 p0 3 p2 0 /int0 9 p0 2 p2 1 /int1 8 p0 1 13 p3 0 7 p0 0 14 p3 1 6 15 d 0 reset k 5 16 d 1 x out 4 17 d 2 x in 3 18 d 3 v ss 2 19 d 4 /cntr0 1 v dd 20 c/cntr1 21 22 23 24 m34571gxfp m34571gx-xxxfp note: either connect an oscillation circuit or connect x in pin to v ss and leave the x out pin open. v dd v ss (note) v pp sclk sda pgm reset : qzrom pin
rev.1.02 may 25, 2007 page 53 of 124 rej03b0179-0102 4571 group fig 54. when using programmer of suisei electronics system co., ltd, connection example 4571 group t_vdd t_vpp t_rxd t_sclk t_pgm/oe/md t_reset gnd reset circuit either connect an oscillation circuit or connect x in pin to v ss and leave the x out pin open. v dd k p0 1 (sda) p0 0 (sclk) p1 0 (pgm) reset vss x in x out note: for the programming circuit, the wiring capacity of each signal pin must not exceed 47 pf. t_busy t_txd 1 k ? n.c.
rev.1.02 may 25, 2007 page 54 of 124 rej03b0179-0102 4571 group data required for qzrom writing orders the following are necessary when ordering a qzrom product shipped after writing: 1. qzrom writing confirmation form* 2. mark specification form* 3. rom data...........mask file * for the qzrom writing confirmation form and the mark specification form, refer to th e ?renesas technology corp.? homepage (http://www.ren esas.com/homepage.jsp). note that we cannot deal with special font marking (customer's trademark etc.) in qzrom microcomputer.
rev.1.02 may 25, 2007 page 55 of 124 rej03b0179-0102 4571 group list of precautions (1) noise and latch-up prevention connect a capacitor on the following condition to prevent noise and latch-up; ? connect a bypass capacitor (approx. 0.1 f) between pins v dd and v ss at the shortest distance, ? equalize its wiring in width and length, and ? use relatively thick wire. port k is also used as v pp pin. accordingly, when using this pin, connect this pin to v ss or v dd . do not leave this pin open. when port is used for key matrix, connect it to v dd through a pull-up resistor. (2) note on power source voltage when the power source voltage va lue of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the s upply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. (3) register initial values 1 the initial value of the following registers are undefined after system is released from reset. af ter system is released from reset, set initial values. ? register z (2 bits) ? register d (3 bits) ? register e (8 bits) (4) register initial values 2 the initial value of the followi ng registers are undefined at ram back-up. after system is returned from ram back-up, set initial values. ? register z (2 bits) ? register x (4 bits) ? register y (4 bits) ? register d (3 bits) ? register e (8 bits) (5) program counter make sure that the pc h does not specify after the last page of the built-in rom. (6) stack registers (sks) stack registers (sks) are eight identical registers, so that subroutines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be careful not to over the stack when performing these operations together. (7) multifunction ? the input of d 4 can be used even when cntr0 (output) is selected. the input/output of d 4 can be used even when cntr0 (input) is selected. be careful when using inputs of both cntr0 and d 4 since the input threshold value of cntr0 pin is different from that of port d 4 . ? ?h? output function of port c can be used even when the cntr1 (output) is used. ? the input/output of p2 0 can be used even when int0 is used. be careful when using inputs of both int0 and p2 0 since the input threshold value of int0 pin is different from that of port p2 0 . ? the input/output of p2 1 can be used even when int1 is used. be careful when using inputs of both int1 and p2 1 since the input threshold value of int1 pin is different from that of port p2 1 . (8) power-on reset when the built-in power-on reset ci rcuit is used, set the time for the supply voltage to rise from 0 v to the minimum voltage of recommended operati ng conditions to 100 s or less. if the rising time exceeds 100 s, connect a capacitor between the reset pin and vss at the shortest distance, and input ?l? level to reset pin until the value of supply voltage reaches the minimum operating voltage. (9) pof instruction when the pof instruction is executed continuously after the epof instruction, system en ters the ram back-up state. note that system cannot enter the ram back-up state when executing only the pof instruction. be sure to disable interrupts by executing the di instruction before executing the epof inst ruction and the pof instruction continuously.
rev.1.02 may 25, 2007 page 56 of 124 rej03b0179-0102 4571 group (10)p2 0 /int0 pin (1) bit 3 of register i1 when the input of the p2 0 /int0 pin is controlled with the bit 3 of register i1 in so ftware, be careful about the following notes. ? depending on the input state of the p2 0 /int0 pin, the external 0 interrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 55) and then, ch ange the bit 3 of register i1. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at l east one instruction (refer to (2) in figure 55). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 55). fig 55. external 0 interrupt program example-1 (2) bit 3 of register i1 when the bit 3 of register i1 is cleared to ?0?, the ram back-up mode is selected and the input of int0 pin is disabled, be careful a bout the following notes. ? when the int0 pin input is disabled (register i1 3 = ?0?), set the key-on wakeup of int0 pin to be invalid (register l1 0 = ?0?) before system enters to the ram back-up mode. (refer to (1) in figure 56). fig 56. external 0 interrupt program example-2 (3) bit 2 of register i1 when the interrupt valid waveform of the p2 0 /int0 pin is changed with the bit 2 of regist er i1 in software, be careful about the following notes. ? depending on the input state of the p2 0 /int0 pin, the external 1 interrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 57) and then, change the bit 2 of register i1 is changed. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at l east one instruction (refer to (2) in figure 57). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 57). fig 57. external 0 interrupt program example-3 ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ...... (1) la 8 ; (1 2 ) ti1a ; control of int0 pin input is changed nop ...................................................... (2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop ...................................................... (3) ? ? ? : these bits are not used here. ? ? ? la 0 ; ( 0 2 ) tl1a ; int0 key-on wakeup disabled .....(1) di epof pof ; ram back-up ? ? ? : these bits are not used here. ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ......(1) la 12 ; (1 2 ) ti1a ; interrupt valid waveform is changed nop .......................................................(2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop .......................................................(3) ? ? ? : these bits are not used here.
rev.1.02 may 25, 2007 page 57 of 124 rej03b0179-0102 4571 group (11)p2 1 /int1 pin (1) bit 3 of register i2 when the input of the p2 1 /int1 pin is controlled with the bit 3 of register i2 in so ftware, be careful about the following notes. ? depending on the input state of the p2 1 /int1 pin, the external 1 interrupt request flag (exf1) may be set when the bit 3 of register i2 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to ?0? (refer to (1) in figure 58) and then, ch ange the bit 3 of register i2. in addition, execute the snz1 instruction to clear the exf1 flag to ?0? after executing at l east one instruction (refer to (2) in figure 58). also, set the nop instruction for the case when a skip is performed with the snz1 instru ction (refer to (3) in figure 58). fig 58. external 1 interrupt program example-1 (2) bit 3 of register i2 when the bit 3 of register i2 is cleared to ?0?, the ram back-up mode is selected and the input of int1 pin is disabled, be careful a bout the following notes. ? when the int1 pin input is disabled (register i2 3 = ?0?), set the key-on wakeup of int1 pin to be invalid (register l2 0 = ?0?) before system enters to the ram back-up mode. (refer to (1) in figure 59) . fig 59. external 1 interrupt program example-2 (3) bit 2 of register i2 when the interrupt valid waveform of the p2 1 /int1 pin is changed with the bit 2 of regist er i2 in software, be careful about the following notes. ? depending on the input state of the p2 1 /int1 pin, the external 1 interrupt request flag (exf1) may be set when the bit 2 of register i2 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register v1 to ?0? (refer to (1) in figure 60) and then, change the bit 2 of register i2 is changed. in addition, execute the snz1 instruction to clear the exf1 flag to ?0? after executing at l east one instruction (refer to (2) in figure 60). also, set the nop instruction for the case when a skip is performed with the snz1 instru ction (refer to (3) in figure 60). fig 60. external 1 interrupt program example-3 ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz1 instruction is valid ...... (1) la 8 ; (1 2 ) ti1a ; control of int1 pin input is changed nop ...................................................... (2) snz0 ; the snz1 instruction is executed (exf1 flag cleared) nop ...................................................... (3) ? ? ? : these bits are not used here. ? ? ? la 0 ; ( 0 2 ) tl1a ; int1 key-on wakeup disabled .....(1) di epof pof ; ram back-up ? ? ? : these bits are not used here. ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz1 instruction is valid ......(1) la 12 ; (1 2 ) ti1a ; interrupt valid waveform is changed nop .......................................................(2) snz0 ; the snz1 instruction is executed (exf1 flag cleared) nop .......................................................(3) ? ? ? : these bits are not used here.
rev.1.02 may 25, 2007 page 58 of 124 rej03b0179-0102 4571 group (12)prescaler stop prescaler counting and then execute the tabps instruction to read its data. stop prescaler counting and then execute the tpsab instruction to write data to prescaler. (13)timer count source stop timer 1, 2 or 3 counting to change its count source. (14)reading the count value stop timer 1, 2 or 3 counting a nd then execute the tab1, tab2 or tab3 instruction to read its data. (15)writing to the timer stop timer 1, 2 or 3 counting and then execute the t1ab, t2ab, t3ab or t3r3l instruction to write data to timer. (16)writing to reload register in order to write a data to the reload register r1 while the timer 1 is operating, execute the tr 1ab instruction except a timing of the timer 1 underflow. in order to write a data to the reload register r3h while the timer 3 is operating, execute the t3hab instruction except a timing of the timer 3 underflow. (17)pwm signal if the timer 3 count stop timing and the timer 3 underflow timing overlap during output of the pwm signal, a hazard may occur in the pwm output waveform. when ?h? interval expansion function of the pwm signal is used, set ?1? or more to reload register r3h. set the port c output latch to ?0 ? to output the pwm signal from c/cntr1 pin. (18)prescaler, timer 1, timer 2 and timer 3 count start timing and count time when operation starts count starts from the first rising edge of the count source (2) in figure 61 after prescaler and tim er operations start (1) in figure 61. time to first underflow (3) in figu re 61 is shorter (for up to 1 period of the count source) than time among next underflow (4) in figure 61 by the timing to start the timer and count source operations after count starts. when selecting cntr0 input as the count source of timer 1, timer 1 operates synchronizing with the count edge (falling edge or rising edge) of cntr0 i nput selected by software. fig 61. timer count start timing and count time when operation starts (19)watchdog timer ? the watchdog timer function is valid after system is released from reset. when not usi ng the watchdog timer function, execute the dwdt instructio n and the wrst instruction continuously, and clear the wef flag to ?0? to stop the watchdog timer function. ? the contents of wdf1 flag and timer wdt are initialized at the ram back-up mode. ? when using the watchdog timer and the ram back-up mode, initialize the wdf1 flag with the wrst instruction just before the microcomputer enters the ram back-up state. also, set the nop instruction after the wrst instruction, for the case when a skip is performed with the wrst instruction. (20)external clock be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). also, note that the ram back-u p mode (pof instruction) cannot be used when using the external clock. (21)qzrom (1) be careful not to apply overvoltage to mcu. the contents of qzrom may be overwritte n because of overvoltage. take care especially at turning on the power. (2) as for the product shippe d in blank, renesas does not perform the writing test to user rom area after the assembly process though the qzrom writing test is performed enough before the asse mbly process. therefore, a writing error of approx.0.1 % may occur. moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing envir onment may cause some writing errors. (22)notes on rom code protect (qzrom product shipped after writing) as for the qzrom product shippe d after writing, the rom code protect is specified according to the rom option setup data in the mask file which is submitted at ordering. the rom option setup data in the mask file is ?00 16 ? for protect enabled or ?ff 16 ? for protect disabled. note that the mask file which has nothing at the rom option data or has the data other than ?00 16 ? and ?ff 16 ? can not be accepted. count source (3) (4) (1) timer start (2) count source (when falling edge of cntr0 input is selected) timer 1 value timer 1 underflow signal 32 1 0 3 2 1 0 3 2
rev.1.02 may 25, 2007 page 59 of 124 rej03b0179-0102 4571 group notes on noise countermeasures against noi se are described below. the following counte rmeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 1. shortest wiring length (1) wiring for reset pin make the length of wiring whic h is connected to the reset pin as short as possible. especially , connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring. in order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the reset pin is required. if noise having a shorter pulse wi dth than this is input to the reset input pin, the reset is releas ed before the internal state of the microcomputer is completely initialized. this may cause a program runaway. fig 62. wiring for the reset pin (2) wiring for cloc k input/output pins ? make the length of wiring whic h is connected to clock i/o pins as short as possible. ? make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ? separate the v ss pattern only for oscillation from other v ss patterns. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. fig 63. wiring for clock i/o pins (3) port k wiring do not leave port k open. always connect it to the v dd pin or v ss pin using the thickest wire at the shortest distance. when port k is used for key matrix, connect it to the v dd pin through a pull-up resistor. in that case too, place a pull-up resistor close to port k and connect it to port k or the v dd pin using the thickest wire at the shortest distance as above. port k is also used as th e power source input pin (v pp pin) for the built-in qzrom. when programming to the qzrom, the impedance of port k is low so that the electric writing current will flow into the qzrom. this allows noise to en ter easily. if noise enters from port k, abnormal instruction co des or data are read from the qzrom, which may caus e a program runaway. fig 64. wiring for port k reset reset circuit noise v ss v ss n.g. reset circuit v ss reset v ss o.k. noise x in x out v ss n.g. x in x out v ss o.k. v dd v ss k shortest distance (note) (note) note: this indicates pin. v dd v ss k shortest distance (note) (note) v dd v ss k shortest distance shortest distance a pull-up resistor (note) (note)
rev.1.02 may 25, 2007 page 60 of 124 rej03b0179-0102 4571 group 2. connection of bypass capacitor across v ss line and v dd line connect an approximately 0.1 f bypass capacitor across the v ss line and the v dd line as follows: ? connect a bypass capacitor across the v ss pin and the v dd pin at equal length. ? connect a bypass capacitor across the v ss pin and the v dd pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v dd line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v dd pin. fig 65. bypass capacitor across the v ss line and the v dd line 3. wiring to analog input pins ? connect an approximately 100 ? to 1 k ? resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. ? connect an approximately 1000 pf capacitor across the v ss pin and the analog input pin. be sides, connect the capacitor to the v ss pin as close as possible. also, connect the capacitor across the analog input pin a nd the vss pin at equal length. signals which is input in an an alog input pin (such as an a/d converter/comparator input pin) are usually output signals from sensor. the sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. this long wiring functions as an antenna which feeds noise into the microcomputer, which causes no ise to an analog input pin. fig 66. analog signal line and a resistor and a capacitor v ss v dd v ss v dd n.g. o.k. thermistor analog input pin (note) n.g. o.k. v ss note : the resistor is used for dividing resistance with a thermistor. microcomputer noise
rev.1.02 may 25, 2007 page 61 of 124 rej03b0179-0102 4571 group 4. oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from bei ng affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. in the system using a microcom puter, there are signal lines for controlling motors, leds, and ther mal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a conn ecting pattern of an oscillator away from signal lines where pote ntial levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. signal lines where potenti al levels change fre quently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such line s cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. fig 67. wiring for a large current signal line fig 68. wiring to a signal line where potential levels change frequently (3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. fig 69. vss pattern on the underside of an oscillator 5. setup fo r i/o ports setup i/o ports using hardware and software as follows: ? connect a resistor of 100 ? or more to an i/o port in series. ? as for an input port, read data several times by a program for checking whether input levels are equal or not. ? as for an output port or an i/o port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. ? rewrite data to pull-up contro l registers at fixed periods. 6. providing of watchdog timer function by software if a microcomputer runs away becau se of noise or others, it can be detected by a software wa tchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following s hows an example of a watchdog timer provided by software. in th e following example, to reset a microcomputer to nor mal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that in terrupt processing is repeated multiple times in a single main routine processing. x in x out v ss m microcomputer mutual inductance large current gnd x in x out v ss cntr do not cross n.g. oscillator wiring pattern example an example of v ss patterns on the underside of a printed circuit board separate the v ss line for oscillation from other v ss lines x in x out v ss
rev.1.02 may 25, 2007 page 62 of 124 rej03b0179-0102 4571 group ? assigns a single word of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main rout ine. the initial value n should satisfy the following condition: n+1 (counts of interrupt processing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. ? watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initia l value n has been set. ? detects that the interrupt processing routine has failed and deter-mines to branch to the pr ogram initialization routine for recovery processing in the following case: if the swdt contents do not ch ange after interrupt processing. ? decrements the swdt contents by 1 at each interrupt processing. ? determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). ? detects that the main routine has failed and determines to branch to the program initia lization routine for recovery processing in the following case: if the swdt contents are not in itialized to the initial value n but continued to decrement and if they reach 0 or less. fig 70. watchdog timer by software n n >0 0 main routine (swdt) n ei main processing (swdt) =n? interrupt processing routine errors interrupt processing routine (swdt) (swdt) ? 1 interrupt processing (swdt) 0? rti return main routine errors
rev.1.02 may 25, 2007 page 63 of 124 rej03b0179-0102 4571 group control registers note 1.?r? represents read enabled, and ?w? represents write enabled. note 2.when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. note 3.when the contents of i2 2 and i2 3 are changed, the external interrupt request flag exf1 may be set. interrupt control register v1 at reset : 0000 2 at ram back-up : 0000 2 r/w tav1/tv1a v1 3 timer 2 interrupt enable bit 0 interrupt disabled (snzt2 instruction is valid) 1 interrupt enabled (snzt2 instruction is invalid) v1 2 timer 1 interrupt enable bit 0 interrupt disabled (snzt1 instruction is valid) 1 interrupt enabled (snzt1 instruction is invalid) v1 1 external 1 interrupt enable bit 0 interrupt disabled (snz1 instruction is valid) 1 interrupt enabled (snz1 instruction is invalid) v1 0 external 0 interrupt enable bit 0 interrupt disabled (snz0 instruction is valid) 1 interrupt enabled (snz0 instruction is invalid) interrupt control register v2 at reset : 0000 2 at ram back-up : 0000 2 r/w tav2/tv2a v2 3 voltage drop detector interrupt enable bit 0 interrupt disabled (snzvd instruction is valid) 1 interrupt enabled (snzvd instruction is invalid) v2 2 not used 0 this bit has no function, but read/write is enabled. 1 v2 1 not used 0 this bit has no function, but read/write is enabled. 1 v2 0 timer 3 interrupt enable bit 0 interrupt disabled (snzt3 instruction is valid) 1 interrupt enabled (snzt3 instruction is invalid) interrupt control register i1 at reset : 0000 2 at ram back-up : state retained r/w tai1/ti1a i1 3 int0 pin input control bit (note 2) 0 int0 pin input disabled 1 int0 pin input enabled i1 2 interrupt valid waveform for int0 pin/ return level selection bit (note 2) 0 falling waveform (?l? level of int0 pin is recognized with the snzi0 instruction)/?l? level 1 rising waveform (?h? level of int0 pin is recognized with the snzi0 instruction)/?h? level i1 1 int0 pin edge detection circuit control bit 0 one-sided edge detected 1 both edges detected i1 0 int0 pin timer 1 control enable bit 0 timer 1 disabled 1 timer 1 enabled interrupt control register i2 at reset : 0000 2 at ram back-up : state retained r/w tai2/ti2a i2 3 int1 pin input control bit (note 3) 0 int0 pin input disabled 1 int0 pin input enabled i2 2 interrupt valid waveform for int1 pin/ return level selection bit (note 3) 0 falling waveform (?l? level of int0 pin is recognized with the snzi1 instruction)/?l? level 1 rising waveform (?h? level of int0 pin is recognized with the snzi1 instruction)/?h? level i2 1 int1 pin edge detection circuit control bit 0 one-sided edge detected 1 both edges detected i2 0 not used 0 this bit has no function, but read/write is enabled. 1
rev.1.02 may 25, 2007 page 64 of 124 rej03b0179-0102 4571 group note 1.?r? represents read enabled, and ?w? represents write enabled. note 2.this function is valid only when the int0 pin/timer 1 control is enabled (i1 0 =?1?) and the timer 1 count start synchronous circuit is selected (w5 3 =?1?). note 3.this function is va lid only when the int0 pin/time r 1 control is enabled (i1 0 =?1?). timer control register pa at reset : 00 2 at ram back-up : 00 2 w tpaa pa 1 prescaler count source selection bit 0 instruction clock (instck) 1 instruction clock di vided by 4 (instck)/4 pa 0 prescaler control bit 0 stop (state initialized) 1operating timer control register w1 at reset : 0000 2 at ram back-up : state retained r/w taw1/tw1a w1 3 timer 1 count auto-stop circuit selection bit (note 2) 0 timer 1 count auto-stop circuit not selected 1 timer 1 count auto-stop circuit selected w1 2 timer 1 control bit 0 stop (state retained) 1operating timer 1 count source selection bits w1 1 w1 0 count source w1 1 0 0 pwm output (pwmout) 0 1 prescaler output (orclk) 1 0 system clock (stck) w1 0 1 1 cntr0 input timer control register w2 at reset : 0000 2 at ram back-up : state retained r/w taw2/tw2a w2 3 cntr0 pin function selection bit 0 timer 1 underflow signal divided by 2 output 1 timer 2 underflow signal divided by 2 output w2 2 timer 2 control bit 0 stop (state retained) 1operating timer 2 count source selection bits w2 1 w2 0 count source w2 1 0 0 pwm output (pwmout) 0 1 prescaler output (orclk) 1 0 system clock (stck) w2 0 1 1 timer 1 underflow signal (t1udf) timer control register w3 at reset : 0000 2 at ram back-up : 0000 2 r/w taw3/tw3a w3 3 cntr1 pin output control bit 0 cntr1 pin output invalid 1 cntr1 pin output valid w3 2 pwm signal ?h? interval expansion function control bit 0 pwm signal ?h? interval ex pansion function invalid 1 pwm signal ?h? interval expansion function valid w3 1 timer 3 control bit 0 stop (state retained) 1operating w3 0 timer 3 count source selection bit 0x in input 1 prescaler output/2 timer control register w5 at reset : 0000 2 at ram back-up : state retained r/w taw5/tw5a w5 3 timer 1 count start synchronous circuit selection bit (note 3) 0 count start synchronous circuit not selected 1 count start synchronous circuit selected w5 2 cntr0 pin input count edge selection bit 0 falling edge 1 rising edge w5 1 cntr 1 pin output auto-control circuit selection bit 0 output auto-control circuit not selected 1 output auto-control circuit selected w5 0 d 4 /cntr0 pin function selection bit 0d 4 (i/o) / cntr0 (input) 1d 4 (input) /cntr0 (i/o)
rev.1.02 may 25, 2007 page 65 of 124 rej03b0179-0102 4571 group note 1.?r? represents read enabled, and ?w? represents write enabled. clock control register mr at reset : 1111 2 at ram back-up : 1111 2 r/w tamr/tmra operation mode selection bits mr 3 mr 2 operation mode mr 3 0 0 through mode (frequency not divided) 0 1 frequency divided by 2 mode 1 0 frequency divided by 4 mode mr 2 1 1 frequency divided by 8 mode mr 1 not used 0 this bit has no function, but read/write is enabled. 1 mr 0 not used 0 this bit has no function, but read/write is enabled. 1 key-on wakeup control register k0 at reset : 0000 2 at ram back-up : state retained r/w tak0/tk0a k0 3 port p0 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 2 port p0 2 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 1 port p0 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 0 port p0 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k1 at reset : 0000 2 at ram back-up : state retained r/w tak1/tk1a k1 3 port p1 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 2 port p1 2 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 1 port p1 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 0 port p1 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k2 at reset : 0000 2 at ram back-up : state retained r/w tak2/tk2a k2 3 not used 0 this bit has no function, but read/write is enabled. 1 k2 2 port k key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k2 1 port p2 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k2 0 port p2 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register l1 at reset : 0000 2 at ram back-up : state retained r/w tal1/tl1a l1 3 int1 pin return condition selection bit 0 return by level 1 return by edge l1 2 int1 pin valid waveform/ level selection bit 0 falling waveform/?l? level 1 rising waveform/?h? level l1 1 int0 pin return condition selection bit 0 return by level 1 return by edge l1 0 int0 pin key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used
rev.1.02 may 25, 2007 page 66 of 124 rej03b0179-0102 4571 group note 1. ?r? represents read enabled, and ?w? represents write enabled. pull-up control register pu0 at reset : 0000 2 at ram back-up : state retained r/w tapu0/tpu0a pu0 3 port p0 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 2 port p0 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 1 port p0 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 0 port p0 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained r/w tapu1/tpu1a pu1 3 port p1 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 2 port p1 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 1 port p1 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 0 port p1 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu2 at reset : 0000 2 at ram back-up : state retained r/w tapu2/tpu2a pu2 3 not used 0 this bit has no function, but read/write is enabled. 1 pu2 2 not used 0 this bit has no function, but read/write is enabled. 1 pu2 1 port p2 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 0 port p2 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on port output structure control register fr0 at reset : 0000 2 at ram back-up : state retained w tfr0a fr0 3 not used 0 this bit has no function, but read/write is enabled. 1 fr0 2 not used 0 this bit has no function, but read/write is enabled. 1 fr0 1 port p3 1 output structure selection bit 0 n-channel open-drain output 1 cmos output fr0 0 port p3 0 output structure selection bit 0 n-channel open-drain output 1 cmos output port output structure control register fr1 at reset : 0000 2 at ram back-up : state retained w tfr1a fr1 3 port d 3 output structure selection bit 0 n-channel open-drain output 1 cmos output fr1 2 port d 2 output structure selection bit 0 n-channel open-drain output 1 cmos output fr1 1 port d 1 output structure selection bit 0 n-channel open-drain output 1 cmos output fr1 0 port d 0 output structure selection bit 0 n-channel open-drain output 1 cmos output
rev.1.02 may 25, 2007 page 67 of 124 rej03b0179-0102 4571 group instructions each instruction is described as follows; 1. index list of in struction function 2. machine instructi ons (index by alphabet) 3. machine instructi ons (index by function) 4. instruction code table the symbols shown below are used in the following list of instruction function and the machine instructions. note 1.the 4571 group just invalidates the next instruction w hen a skip is performed. the contents of program counter is not in creased by 2. accordingly, the nu mber of cycles does not change even if skip is no t performed. however, t he cycle count becomes ?1? if the tabp p, rt, or rts instruction is skipped. symbol symbol contents symbol contents a register a (4 bits) t1f timer 1 interrupt request flag b register b (4 bits) t2f timer 2 interrupt request flag dr register dr (3 bits) t3f timer 3 interrupt request flag e register e (8 bits) wdf1 watchdog timer flag v1 interrupt control register v1 (4 bits) wef watchdog timer enable flag v2 interrupt control register v2 (4 bits) inte interrupt enable flag i1 interrupt control register i1 (4 bits) exf0 external 0 interrupt request flag i2 interrupt control register i2 (4 bits) exf1 external 1 interrupt request flag pa timer control register pa (2 bits) vdf volt age drop detection circuit interrupt request flag w1 timer control register w1 (4 bits) p power down flag w2 timer control register w2 (4 bits) d port d (5 bits) w3 timer control register w3 (4 bits) p0 port p0 (4 bits) w5 timer control register w5 (4 bits) p1 port p1 (4 bits) mr clock control regist er mr (4 bits) p2 port p2 (2 bits) k0 key-on wakeup control register k0 (4 bits) p3 port p3 (2 bits) k1 key-on wakeup control register k1 (4 bits) k2 key-on wakeup control register k2 (4 bits) x hexadecimal variable l1 key-on wakeup control register l1 (4 bits) y hex adecimal variable pu0 pull-up control register pu0 (4 bits) z hexadec imal variable pu1 pull-up control register pu1 (4 bits) p hexadec imal variable pu2 pull-up control register pu2 (4 bits) n hexadecimal constant fr0 port output structure control regist er fr0 (4 bits) i h exadecimal constant fr1 port output structure control regist er fr1 (4 bits) j h exadecimal constant x register x (4 bits) a 3 a 2 a 1 a 0 binary notation of hexadecimal variable a (same for others) y register y (4 bits) z register z (2 bits) dp data pointer (10 bits) (it consists of registers x, y, and z) direction of data movement ( ) contents of registers and memories pc program counter (14 bits) ? negate, flag unchanged after executing instruction pc h high-order 7 bits of program counter m (dp) ram address pointed by the data pointer pc l low-order 7 bits of program counter a label indi cating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 sk stack register (14 bits 8) p, a label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 6 p 5 p 4 p 3 p 2 p 1 p 0 sp stack pointer (3 bits) cy carry flag rps prescaler reload register (8 bits) c hex. c + hex. number x (also same for others) r1l timer 1 reload register (8 bits) + r2 timer 2 reload register (8 bits) x r3l timer 3 reload register (8 bits ) ? decision of state shown before ??? r3h timer 3 reload register (8 bits) data exchange between a register and memory ps prescaler t1 timer 1 and logical multiplication t2 timer 2 or logical addition t3 timer 3
rev.1.02 may 25, 2007 page 68 of 124 rej03b0179-0102 4571 group m34571g4: p=0 to 31 m34571g6: p=0 to 47 m34571gd: p=0 to 127 index list of instruction function group ing mnemonic function page register to register transfer tab (a) (b) 88, 103 tba (b) (a) 95, 103 tay (a) (y) 95, 103 tya (y) (a) 101, 103 teab (e 7 ? e 4 ) (b) (e 3 ? e 0 ) (a) 96, 103 tabe (b) (e 7 ? e 4 ) (a) (e 3 ? e 0 ) 89, 103 tda (dr 2 ? dr 0 ) (a 2 ? a 0 ) 95, 103 tad (a 2 ? a 0 ) (dr 2 ? dr 0 ) (a 3 ) 0 90, 103 taz (a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 95, 103 tax (a) (x) 94, 103 tasp (a 2 ? a 0 ) (sp 2 ? sp 0 ) (a 3 ) 0 93, 103 ram addresses lxy x, y (x) x, x = 0 to 15 (y) y, y = 0 to 15 77, 103 lz z (z) z, z = 0 to 3 77, 103 iny (y) (y) + 1 76, 103 dey (y) (y) ? 1 74, 103 ram to register transfer tam j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 91, 103 xam j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 102, 103 xamd j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ? 1 102, 103 xami j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 102, 103 tma j (m(dp)) (a) (x) (x)exor(j) j = 0 to 15 98, 103 group ing mnemonic function page arithmetic operation la n (a) n n = 0 to 15 76, 105 tabp p (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) (uptf) = 1, (dr 2 ) 0 (dr 1 , dr 0 ) (rom(pc)) 9 , 8 (b) (rom(pc)) 7 ? 4 (a) (rom(pc)) 3 ? 0 (pc) (sk(sp)) (sp) (sp) ? 1 89, 105 am (a) (a) + (m(dp)) 71, 105 amc (a) (a) + (m(dp)) + (cy) (cy) carry 71, 105 a n (a) (a) + n n = 0 to 15 71, 105 and (a) (a)and(m(dp)) 71, 105 or (a) (a)or(m(dp)) 78, 105 sc (cy) 1 82, 105 rc (cy) 0 80, 105 szc (cy) = 0 ? 86, 105 cma (a) (a) 73, 105 rar 79, 105 bit operation sb j (mj(dp)) 1 j = 0 to 3 81, 105 rb j (mj(dp)) 0 j = 0 to 3 79, 105 szb j (mj(dp)) = 0 ? j = 0 to 3 86, 105 comparison operation seam (a) = (m(dp)) ? 83, 107 sea n (a) = n n = 0 to 15 83, 107 branch operation b a (pc l ) a 6 ? a 0 72, 107 bl p, a (pc h ) p (pc l ) a 6 ? a 0 72, 107 bla p (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 72, 107 cy a 3 a 2 a 1 a 0
rev.1.02 may 25, 2007 page 69 of 124 rej03b0179-0102 4571 group m34571g4: p=0 to 31 m34571g6: p=0 to 47 m34571gd: p=0 to 127 index list of instructio n function (continued) group ing mnemonic function page subroutine operation bm a (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? a 0 72, 107 bml p, a (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) a 6 ? a 0 73, 107 bmla p (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 73, 107 return operation rti (pc) (sk(sp)) (sp) (sp) ? 1 81, 107 rt (pc) (sk(sp)) (sp) (sp) ? 1 80, 107 rts (pc) (sk(sp)) (sp) (sp) ? 1 81, 107 interrupt operation di (inte) 0 74, 109 ei (inte) 1 74, 109 snz0 v1 0 = 0 : (exf0) = 1 ? (exf0) 0 v1 0 = 1 : nop 83, 109 snzi0 i1 2 = 0 : (int0) = ?l? ? i1 2 = 1 : (int0) = ?h? ? 84, 109 snz1 v1 1 = 0 : (exf1) = 1 ? (exf1) 0 v1 1 = 1 : nop 83, 109 snzi1 i2 2 = 0 : (int1) = ?l? ? i2 2 = 1 : (int1) = ?h? ? 84, 109 tav1 (a) (v1) 93, 109 tv1a (v1) (a) 100, 109 tav2 (a) (v2) 93, 109 tv2a (v2) (a) 100, 109 tai1 (a) (i1) 90, 109 ti1a (i1) (a) 96, 109 tai2 (a) (i2) 90, 109 ti2a (i2) (a) 97, 109 group ing mnemonic function page timer operation tpaa (pa 0 ) (a 0 ) 98, 109 taw1 (a) (w1) 93, 109 tw1a (w1) (a) 100, 109 taw2 (a) (w2) 94, 109 tw2a (w2) (a) 101, 109 taw3 (a) (w3) 94, 109 tw3a (w3) (a) 101, 109 taw5 (a) (w5) 94, 109 tw5a (w5) (a) 101, 109 tabps (b) (tps 7 ? tps 4 ) (a) (tps 3 ? tps 0 ) 89, 111 tpsab (rps 7 ? rps 4 ) (b) (tps 7 ? tps 4 ) (b) (rps 3 ? rps 0 ) (a) (tps 3 ? tps 0 ) (a) 99, 111 tab1 (b) (t1 7 ? t1 4 ) (a) (t1 3 ? t1 0 ) 88, 111 t1ab (r1 7 ? r1 4 ) (b) (t1 7 ? t1 4 ) (b) (r1 3 ? r1 0 ) (a) (t1 3 ? t1 0 ) (a) 87, 111 tr1ab (r1 7 ? r1 4 ) (b) (r1 3 ? r1 0 ) (a) 100, 111 tab2 (b) (t2 7 ? t2 4 ) (a) (t2 3 ? t2 0 ) 88, 111 t2ab (r2 7 ? r2 4 ) (b) (t2 7 ? t2 4 ) (b) (r2 3 ? r2 0 ) (a) (t2 3 ? t2 0 ) (a) 87, 111 tab3 (b) (t3 7 ? t3 4 ) (a) (t3 3 ? t3 0 ) 89, 111 t3ab (r3l 7 ? r3l 4 ) (b) (t3 7 ? t3 4 ) (b) (r3l 3 ? r3l 0 ) (a) (t3 3 ? t3 0 ) (a) 87, 111 t3r3l (t3 7 ? t3 0 ) (r3l 7 ? r3l 0 ) 88, 111 t3hab (r3h 7 ? r3h 4 ) (b) (r3h 3 ? r3h 0 ) (a) 87, 111
rev.1.02 may 25, 2007 page 70 of 124 rej03b0179-0102 4571 group index list of instructio n function (continued) group ing mnemonic function page timer operation snzt1 v1 2 = 0 : (t1f) = 1 ? (t1f) 0 v1 2 = 1 : snzt1=nop 84, 111 snzt2 v1 3 = 0 : (t2f) = 1 ? (t2f) 0 v1 3 = 1 : snzt2=nop 85, 111 snzt3 v2 0 = 0 : (t3f) = 1 ? (t3f) 0 v2 0 = 1 : snzt3=nop 85, 111 input/output operation iap0 (a) (p0) 75, 113 op0a (p0) (a) 77, 113 iap1 (a) (p1) 75, 113 op1a (p1) (a) 78, 113 iap2 (a 1 , a 0 ) (p2 1 , p2 0 ) (a 3 , a 2 ) 0 76, 113 op2a (p2 1 , p2 0 ) (a 1 , a 0 ) 78, 113 iap3 (a 1 , a 0 ) (p3 1 , p3 0 ) (a 3 , a 2 ) 0 76, 113 op3a (p3 1 , p3 0 ) (a 1 , a 0 ) 78, 113 cld (d) 1 73, 113 rd (d(y)) 0 (y) = 0 to 4 80, 113 sd (d(y)) 1 (y) = 0 to 4 82, 113 szd (d(y)) = 0 ? (y) = 0 to 4 86, 113 rcp (c) (0) 80, 113 scp (c) (1) 82, 113 iak (a 0 ) (k) (a 3 ? a 1 ) 0 75, 113 tfr0a (fr0) (a) 96, 113 tfr1a (fr1) (a) 96, 113 tapu0 (a) (pu0) 92, 113 tpu0a (pu0) (a) 99, 113 tapu1 (a) (pu1) 92, 113 tpu1a (pu1) (a) 99, 113 tapu2 (a) (pu2) 92, 113 tpu2a (pu2) (a) 99, 113 group ing mnemonic function page input/output operation tak0 (a) (k0) 90, 115 tk0a (k0) (a) 97, 115 tak1 (a) (k1) 91, 115 tk1a (k1) (a) 97, 115 tak2 (a) (k2) 91, 115 tk2a (k2) (a) 97, 115 tal1 (a) (l1) 91, 115 tl1a (l1) (a) 98, 115 other operation tamr (a) (mr) 92, 115 tmra (mr) (a) 98, 115 nop (pc) (pc)+1 77, 115 pof ram back-up 79, 115 epof pof instruction valid 75, 115 snzp (p) = 1 ? 84, 115 snzvd v2 3 = 0 : (vdf) = 1? v2 3 = 0 : nop 85, 115 wrst (wdf1) = 1 ? (wdf 1 ) 0 102, 115 dwdt stop of watchdog timer function enabled 74, 115 srst system reset 85, 115 rupt (uptf) 0 81, 115 supt (uptf) 1 86, 115 rbk p 6 0 when tabp p instruction is executed 79, 115 sbk p 6 1 when tabp p instruction is executed 82, 115
rev.1.02 may 25, 2007 page 71 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) a n (add n and accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 000110nnnn 2 06n 16 11 - overflow = 0 opera- tion: (a) (a) + n n = 0 to 15 grouping: arithmetic operation description: adds the value n in t he immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction w hen there is overflow as the result of operation. am (add accumulator and memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001010 2 00a 16 11 - - opera- tion: (a) (a)?{(m(dp)) grouping: arithmetic operation description: adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. amc (add accumulator, memory and carry) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001011 2 00b 16 110/1 - opera- tion: (a) (a) + (m(dp)) + (cy) (cy) carry grouping: arithmetic operation description: adds the contents of m( dp) and carry flag cy to register a. stores the result in register a and carry flag cy. and (logical and between accumulator and memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011000 2 018 16 11 - - opera- tion: (a) (a) and (m(dp)) grouping: arithmetic operation description: takes the and operati on between the contents of register a and the contents of m(dp), and stores the result in regis- ter a.
rev.1.02 may 25, 2007 page 72 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) b a (branch to address a) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 1 8 +a a 16 11 - - opera- tion: (pc l ) a 6 to a 0 grouping: branch operation description: branch within a page : branches to address a in the identi- cal page. note: specify the branch address within the page including this instruction. bl p,a (branch long to address a in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00111p 4 p 3 p 2 p 1 p 0 2 0 e +p p 16 2 2 - - 1p 6 p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 2aa 16 grouping: branch operation description: branch out of a page : branches to address a in page p. note: m34571g4 : p = 0 to 31 m34571g6 : p = 0 to 47 m34571gd : p = 0 to 127 opera- tion: (pc h ) p (pc l ) a 6 to a 0 bla p (branch long to address (d)+(a) in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010000 2 010 16 22 - - 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 2 2pp 16 grouping: branch operation description: branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: m34571g4 : p = 0 to 31 m34571g6 : p = 0 to 47 m34571gd : p = 0 to 127 opera- tion: (pc h ) p (pc l ) (dr 2 ? r 0 , a 3 ? a 0 ) bm a (branch and mark to address a in page 2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 1aa 16 11 - - opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? a 0 grouping: subroutine call operation description: call the subroutine in page 2 : calls the subroutine at address a in page 2. note: subroutine extending from page 2 to another page can also be called with the bm instruction when it starts on page 2. be careful not to over the stack because the maximum level of subroutine nesting is 8.
rev.1.02 may 25, 2007 page 73 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) bml p,a (branch and mark long to address a in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00110p 4 p 3 p 2 p 1 p 0 2 0 c + p p 16 22 - - 1p 6 p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 2aa 16 grouping: subroutine call operation description: call the subroutine : ca lls the subroutine at address a in page p. note: m34571g4 : p = 0 to 31 m34571g6 : p = 0 to 47 m34571gd : p = 0 to 127 be careful not to over the stack because the maximum level of subroutine nesting is 8. opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) a 6 ? a 0 bmla p (branch and mark long to address (d)+(a) in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000110000 2 030 16 22 - - 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 2 2pp 16 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: m34571g4 : p = 0 to 31 m34571g6 : p = 0 to 47 m34571gd : p = 0 to 127 be careful not to over the stack because the maximum level of subroutine nesting is 8. opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) cld (clear port d) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010001 2 011 16 11 - - opera- tion: (d) (1) grouping: input/output operation description: sets (1) to port d. cma (complement of accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011100 2 01c 16 11 - - opera- tion: (a) (a ) grouping: arithmetic operation description: stores the one?s complement for register a?s contents in register a.
rev.1.02 may 25, 2007 page 74 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) dey (decrement register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010111 2 017 16 11 - (y) = 15 opera- tion: (y) (y) ? 1 grouping: ram addresses description: subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. di (disable interrupt) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000100 2 004 16 11 - - opera- tion: (inte) 0 grouping: interrupt control operation description: clears (0) to interrupt enable flag inte, and disables the interrupt. note: interrupt is disabled by ex ecuting the di instruction after executing 1 machine cycle. dwdt (disable watchdog timer) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010011100 2 29c 16 11 - - opera- tion: stop of watchdog timer function enabled grouping: other operation description: stops the watchdog timer f unction by the wrst instruction after executing the dwdt instruction. ei (enable interrupt) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000101 2 005 16 11 - - opera- tion: (inte) 1 grouping: interrupt control operation description: sets (1) to interrupt enable flag inte, and enables the interrupt. note: interrupt is enabled by executing the ei instruction after executing 1 machine cycle.
rev.1.02 may 25, 2007 page 75 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) epof (enable pof instruction) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001011011 2 05b 16 11 - - opera- tion: pof instruction valid grouping: other operation description: makes the immediate afte r pof instruction valid by exe- cuting the epof instruction. iak (input accumulator from port k) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001101111 2 26f 16 11 - - opera- tion: (a 0 ) (k) (a 3 ? a 1 ) 0 grouping: input/output operation description: transfers the input of por t k to the least significant bit (a 0 ) of register a. ?0? is stored to the high-order 3 bits (a 3 ? a 1 ) of register a. iap0 (input accumulator from port p0) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100000 2 260 16 11 - - opera- tion: (a) (p0) grouping: input/output operation description: transfers the input of port p0 to register a. iap1 (input accumulator from port p1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100001 2 261 16 11 - - opera- tion: (a) (p1) grouping: input/output operation description: transfers the input of port p1 to register a.
rev.1.02 may 25, 2007 page 76 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) iap2 (input accumulator from port p2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100010 2 262 16 11 - - opera- tion: (a 1 , a 0 ) (p2 1 , p2 0 ) (a 3 , a 2 ) 0 grouping: input/output operation description: transfers the input of port p2 to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. iap3 (input accumulator from port p3) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100011 2 263 16 11 - - opera- tion: (a 1 , a 0 ) (p3 1 , p3 0 ) (a 3 , a 2 ) 0 grouping: input/output operation description: transfers the input of port p3 to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. iny (increment register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010011 2 013 16 11 - (y) = 0 opera- tion: (y) (y) + 1 grouping: ram addresses description: adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of r egister y is not 0, the next instruction is executed. la n (load n in accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 000111nnnn 2 07n 16 11 - continuous description opera- tion: (a) n n = 0 to 15 grouping: arithmetic operation description: loads the value n in the immediate field to register a. when the la instructions are continuously coded and exe- cuted, only the first la instruction is executed and other la instructions coded continuously are skipped.
rev.1.02 may 25, 2007 page 77 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) lxy x,y (load register x and y with x and y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 2 3xy 16 11 - continuous description opera- tion: (x) x x = 0 to 15 (y) y y = 0 to 15 grouping: ram addresses description: loads the value x in the immediate field to register x, and the value y in the immediate fi eld to register y. when the lxy instructions are c ontinuously c oded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. lz z (load register z with z) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00010010z 1 z 0 2 04 8 +z 16 1 1 - - opera- tion: (z) z z = 0 to 3 grouping: ram addresses description: loads the value z in t he immediate field to register z. nop (no operation) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000000 2 000 16 11 - - opera- tion: (pc) (pc) + 1 grouping: other operation description: no operation; adds 1 to program counter value, and others remain unchanged. op0a (output port p0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100000 2 220 16 11 - - opera- tion: (p0) (a) grouping: input/output operation description: outputs the contents of register a to port p0.
rev.1.02 may 25, 2007 page 78 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) op1a (output port p1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100001 2 221 16 11 - - opera- tion: (p1) (a) grouping: input/output operation description: outputs the contents of register a to port p1. op2a (output port p2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100010 2 222 16 11 - - opera- tion: (p2 1 , p2 0 ) (a 1 , a 0 ) grouping: input/output operation description: outputs the contents of the low-order 2 bits (a 1 , a 0 ) of reg- ister a to port p2. op3a (output port p3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100011 2 223 16 11 - - opera- tion: (p3 1 , p3 0 ) (a 1 , a 0 ) grouping: input/output operation description: outputs the contents of the low-order 2 bits (a 1 , a 0 ) of reg- ister a to port p3. or (logical or between accumulator and memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011001 2 019 16 11 - - opera- tion: (a) (a) or (m(dp)) grouping: arithmetic operation description: takes the or operation between the contents of register a and the contents of m(dp), and stores the result in register a.
rev.1.02 may 25, 2007 page 79 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) pof (power off) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000010 2 002 16 11 - - opera- tion: ram back-up grouping: other operation description: puts the system in ra m back-up state by executing the pof instruction after executing the epof instruction. note: if the epof instruction is not executed just before this instruction, this instruction is equivalent to the nop instruc- tion. rar (rotate accumulator right) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011101 2 01d 16 110/1 - opera- tion: grouping: arithmetic operation description: rotates 1 bit of the c ontents of register a including the contents of carry flag cy to the right. rb j (reset bit) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00010011 j j 2 04 c +j 16 1 1 - - opera- tion: (mj(dp)) 0 j = 0 to 3 grouping: bit operation description: clears (0) the contents of bi t j (bit specified by the value j in the immediate field) of m(dp). rbk ( reset bank flag) ) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001001100 2 040 16 11 - - opera- tion: p 6 0 when tabp p instruction is executed. grouping: other operation description: sets referring data area to pages 0 to 63 when the tabp p instruction is executed. this in struction is valid only for the tabp p instruction. note: this instruction cannot be used for the m34571g4/g6. cy a 3 a 2 a 1 a 0
rev.1.02 may 25, 2007 page 80 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) rc (reset carry flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000110 2 006 16 110 - opera- tion: (cy) 0 grouping: arithmetic operation description: clears (0) to carry flag cy. rcp (reset port c) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010001100 2 28c 16 11 - - opera- tion: (c) 0 grouping: input/output operation description: clears (0) to port c. rd (reset port d specified by register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010100 2 014 16 11 - - opera- tion: (d(y)) 0 however, (y) = 0 to 4 grouping: input/output operation description: clears (0) to a bit of port d specified by register y. note: (y) = 0 to 4. do not execute this instructi on if values except above are set to register y. rt (return from subroutine) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001000100 2 044 16 12 - - opera- tion: (pc) (sk(sp)) (sp) (sp) ? 1 grouping: return operation description: returns from subroutine to the routine called the subrou- tine.
rev.1.02 may 25, 2007 page 81 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) rti (return from interrupt) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001000110 2 046 16 12 - - opera- tion: (pc) (sk(sp)) (sp) (sp) ? 1 grouping: return operation description: returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy instruction, register a and register b to the states just before interrupt. rts (return from subroutine and skip) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001000101 2 045 16 1 2 - skip at uncondition opera- tion: (pc) (sk(sp)) (sp) (sp) ? 1 grouping: return operation description: returns from subroutine to the routine called the subrou- tine, and skips the next instruction at uncondition. rupt (reset upt flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001011000 2 058 16 11 - - opera- tion: (uptf) 0 grouping: other operation description: clears (0) to the hi gh-order bit reference enable flag uptf. note: even when the table reference instruction (tabp p) is exe- cuted, the high-order 2 bits of rom reference data is not transferred to register d. sb j (set bit) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00010111 j j 2 05 c +j 16 11 - - opera- tion: (mj(dp)) 1 j = 0 to 3 grouping: bit operation description: sets (1) the contents of bi t j (bit specified by the value j in the immediate field) of m(dp).
rev.1.02 may 25, 2007 page 82 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) sbk (set bank flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001000001 2 041 16 11 - - opera- tion: p 6 1 when tabp p instruction is executed. grouping: other operation description: sets referring data area to pages 64 to 127 when the tabp p instruction is executed. this instruction is valid only for the tabp p instruction. note: this instruction cannot be used for the m34571g4/g6. sc (set carry flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000111 2 007 16 111 - opera- tion: (cy) 1 grouping: arithmetic operation description: sets (1) to carry flag cy. scp (set port c) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010001101 2 28d 16 11 - - opera- tion: (c) 1 grouping: input/output operation description: sets (1) to port c. sd (set port d specified by register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010101 2 015 16 11 - - opera- tion: (d(y)) 1 (y) = 0 to 4 grouping: input/output operation description: sets (1) to a bit of port d specified by register y. note: (y) = 0 to 4. do not execute this instructi on if values except above are set to register y.
rev.1.02 may 25, 2007 page 83 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) sea n (skip equal, accumulator with immediate data n) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000100101 2 025 16 22 - (a) = n n = 0 to 15 000111nnnn 2 07n 16 grouping: comparison operation description: skips the next instruction when the contents of register a is equal to the value n in the immediate field. executes the next instruction when the contents of register a is not equal to the val ue n in the immediate field. opera- tion: (a) = n ? n = 0 to 15 seam (skip equal, accumulator with memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000100110 2 026 16 1 1 - (a) = (m(dp)) opera- tion: (a) = (m(dp)) ? grouping: comparison operation description: skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of register a is not equal to the contents of m(dp). snz0 (skip if non zero condition of external interrupt 0 request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111000 2 038 16 11 -v1 0 = 0 : (exf0) = 1 opera- tion: v1 0 = 0 : (exf0) = 1 ? (exf0) 0 v1 0 = 1 : snz0 = nop (v1 0 : bit 0 of the interrupt control register v1) grouping: interrupt operation description: when v1 0 = 0 : clears (0) to the exf0 flag and skips the next instruction when exter nal 0 interrupt request flag exf0 is ?1?. when the exf0 flag is ?0?, executes the next instruction. when v1 0 = 1 : this instruction is equivalent to the nop instruction. snz1 (skip if non zero condition of external interrupt 1 request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111001 2 039 16 11 -v1 1 = 0 : (exf1) = 1 opera- tion: v1 1 = 0 : (exf1) = 1 ? (exf1) 0 v1 1 = 1 : snz1 = nop (v1 1 : bit 1 of the interrupt control register v1) grouping: interrupt operation description: when v1 1 = 0 : clears (0) to the exf1 flag and skips the next instruction when exter nal 1 interrupt request flag exf1 is ?1?. when the exf1 flag is ?0?, executes the next instruction. when v1 1 = 1 : this instruction is equivalent to the nop instruction.
rev.1.02 may 25, 2007 page 84 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) snzi0 (skip if non zero condition of external interrupt 0 input pin) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111010 2 03a 16 11 - i1 2 = 0 : (int0) = ?l? i1 2 = 1 : (int0) = ?h? opera- tion: i1 2 = 0 : (int0) = ?l? ? i1 2 = 1 : (int0) = ?h? ? (i1 2 : bit 2 of the interrupt control register i1) grouping: interrupt operation description: when i1 2 = 0 : skips the next instruction when the level of int0 pin is ?l?. executes the next instruction when the level of int0 pin is ?h?. when i1 2 = 1 : skips the next instruction when the level of int0 pin is ?h.? executes the next instruction when the level of int0 pin is ?l?. snzi1 (skip if non zero condition of external interrupt 1 input pin) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111011 2 03b 16 11 - i2 2 = 0 : (int1) = ?l? i2 2 = 1 : (int1) = ?h? opera- tion: i2 2 = 0 : (int1) = ?l? ? i2 2 = 1 : (int1) = ?h? ? grouping: interrupt operation description: when i2 2 = 0 : skips the next instruction when the level of int1 pin is ?l?. executes the next instruction when the level of int1 pin is ?h?. when i2 2 = 1 : skips the next instruction when the level of int1 pin is ?h?. executes the next instruction when the level of int1 pin is ?l?. snzp (skip if non zero condition of power down flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000011 2 003 16 11 - (p) = 1 opera- tion: (p) = 1 ? grouping: other operation description: skips the next instruction when the p flag is ?1?. after skipping, the p flag remains unchanged. executes the next instruction when the p flag is ?0?. snzt1 (skip if non zero condition of timer 1 interrupt request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010000000 2 280 16 11 -v1 2 = 0 : (t1f) = 1 opera- tion: v1 2 = 0 : (t1f) = 1 ? (t1f) 0 v1 2 = 1 : snzt1 = nop (v1 2 = bit 2 of interrupt control register v1) grouping: timer operation description: when v1 2 = 0 : clears (0) to the t1f flag and skips the next instruction when timer 1 interrupt request flag t1f is ?1?. when the t1f flag is ?0,? executes the next instruction. when v1 2 = 1 : this instruction is equivalent to the nop instruction.
rev.1.02 may 25, 2007 page 85 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) snzt2 (skip if non zero condition of timer 2 interrupt request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010000001 2 281 16 11 -v1 3 = 0 : (t2f) = 1 opera- tion: v1 3 = 0 : (t2f) = 1 ? (t2f) 0 v1 3 = 1 : snzt2 = nop (v1 3 = bit 3 of interrupt control register v1) grouping: timer operation description: when v1 3 = 0 : clears (0) to the t2f flag and skips the next instruction when timer 2 interrupt request flag t2f is ?1?. when the t2f flag is ?0?, executes the next instruction. when v1 3 = 1 : this instruction is equivalent to the nop instruction. snzt3 (skip if non zero condition of timer 3 interrupt request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010000010 2 282 16 11 -v2 0 = 0 : (t3f) = 1 opera- tion: v2 0 = 0 : (t3f) = 1 ? (t3f) 0 v2 0 = 1 : snzt3 = nop grouping: timer operation description: when v2 0 = 0 : clears (0) to the t3f flag and skips the next instruction when timer 3 interrupt request flag t3f is ?1?. when the t3f flag is ?0?, executes the next instruction. when v2 0 = 1 : this instruction is equivalent to the nop instruction. snzvd (skip if non zero condition of voltage detector interrupt request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010001010 2 28a 16 11 -v2 3 = 0 : (vdf) = 1 opera- tion: v2 3 = 0 : (vdf) = 1? v2 3 = 1 : snzvd = nop grouping: other operation description: when v2 3 = 0 : skips the next instruction when voltage detector interrupt request flag vdf is ?1?. after skipping, clears (0) to the vdf flag. the vdf flag is not cleared to ?0?. when v2 3 = 1 : this instruction is equivalent to the nop instruction. srst (system reset) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000001 2 001 16 11 - - opera- tion: system reset grouping: other operation description: system reset occurs.
rev.1.02 may 25, 2007 page 86 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) supt (set upt flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001011001 2 059 16 11 - - opera- tion: (uptf) 1 grouping: other operation description: sets (1) to the high- order bit reference enable flag uptf. note: when the table reference inst ruction (tabp p) is executed, the high-order 2 bits of rom reference data is transferred to the low-order 2 bits of register d. szb j (skip if zero, bit) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00001000 j j 2 02 j 16 11 - (mj(dp)) = 0 j = 0 to 3 opera- tion: (mj(dp)) = 0 ? j = 0 to 3 grouping: bit operation description: skips the next instruction when the contents of bit j (bit specified by the value j in t he immediate field) of m(dp) is ?0?. executes the next instruction when the contents of bit j of m(dp) is ?1?. szc (skip if zero, carry flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000101111 2 02f 16 11 - (cy) = 0 opera- tion: (cy) = 0 ? grouping: arithmetic operation description: skips the next instruct ion when the contents of carry flag cy is ?0?. after skipping, the cy flag remains unchanged. executes the next instruction when the contents of the cy flag is ?1?. szd (skip if zero, port d specified by register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000100100 2 024 16 2 2 - (d(y)) = 0 0000101011 2 02b 16 grouping: input/output operation description: skips the next instructi on when a bit of port d specified by register y is ?0?. executes t he next instruction when the bit is ?1?. note: (y) = 0 to 4. do not execute this instructi on if values except above are set to register y. opera- tion: (d(y)) = 0 ? (y) = 0 to 4
rev.1.02 may 25, 2007 page 87 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) t1ab (transfer data to timer 1 and register r1 from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110000 2 230 16 11 - - opera- tion: (t1 7 ? t1 4 ) (b) (r1 7 ? r1 4 ) (b) (t1 3 ? t1 0 ) (a) (r1 3 ? r1 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 reload register r1. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. t2ab (transfer data to timer 2 and register r2 from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110001 2 231 16 11 - - opera- tion: (t2 7 ? t2 4 ) (b) (r2 7 ? r2 4 ) (b) (t2 3 ? t2 0 ) (a) (r2 3 ? r2 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 reload register r2. transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. t3ab (transfer data to timer 3 and register r3l from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110010 2 232 16 11 - - opera- tion: (t3 7 ? t3 4 ) (b) (r3l 7 ? r3l 4 ) (b) (t3 3 ? t3 0 ) (a) (r3l 3 ? r3l 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 3 and timer 3 reload register r3l. transfers the contents of register a to the low-order 4 bits of timer 3 and timer 3 reload register r3l. t3hab (transfer data to register r3h from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000111101 2 23d 16 11 - - opera- tion: (r3h 7 ? r3h 4 ) (b) (r3h 3 ? r3h 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 3 and timer 3 reload register r3h. transfers the contents of register a to the low-order 4 bits of timer 3 and timer 3 reload register r3h.
rev.1.02 may 25, 2007 page 88 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) t3r3l (transfer data to timer 3 from register r3l) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110100 2 234 16 11 - - opera- tion: (t3 7 ? t3 0 ) (r3l 7 ? r3l 0 ) grouping: timer operation description: transfers the contents of reload register r3l to timer 3. tab (transfer data to accumulator from register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011110 2 01e 16 11 - - opera- tion: (a) (b) grouping: register to register transfer description: transfers the contents of register b to register a. tab1 (transfer data to accumulato r and register b from timer 1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001110000 2 270 16 11 - - opera- tion: (b) (t1 7 ? t1 4 ) (a) (t1 3 ? t1 0 ) grouping: timer operation description: transfers the high-order 4 bits (t1 7 ? t1 4 ) of timer 1 to reg- ister b. transfers the low-order 4 bits (t1 3 ? t1 0 ) of timer 1 to regis- ter a. tab2 (transfer data to accumulato r and register b from timer 2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001110001 2 271 16 11 - - opera- tion: (b) (t2 7 ? t2 4 ) (a) (t2 3 ? t2 0 ) grouping: timer operation description: transfers the high-order 4 bits (t2 7 ? t2 4 ) of timer 2 to reg- ister b. transfers the low-order 4 bits (t2 3 ? t2 0 ) of timer 2 to regis- ter a.
rev.1.02 may 25, 2007 page 89 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tab3 (transfer data to accumulato r and register b from timer 3) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001110010 2 272 16 11 - - opera- tion: (b) (t3 7 ? t3 4 ) (a) (t3 3 ? t3 0 ) grouping: timer operation description: transfers the high-order 4 bits (t3 7 ? t3 4 ) of timer 3 to reg- ister b. transfers the low-order 4 bits (t3 3 ? t3 0 ) of timer 3 to regis- ter a. tabe (transfer data to accumulator and register b from register e) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000101010 2 02a 16 11 - - opera- tion: (b) (e 7 ? e 4 ) (a) (e 3 ? e 0 ) grouping: register to register transfer description: transfers the high-order 4 bits (e 7 ? e 4 ) of register e to reg- ister b, and low-order 4 bits of register e to register a. tabp p (transfer data to accumulator and register b from program memory in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0010p 5 p 4 p 3 p 2 p 1 p 0 2 0 8 +p p 16 13 - - opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) (b) (rom(pc)) 7 ? 4 (a) (rom(pc)) 3 ? 0 (uptf) 1 (dr 1 , dr 0 ) (rom(pc)) 9 , 8 (dr 2 ) 0 (pc) (sk(sp)) (sp) (sp) ? 1 grouping: arithmetic operation description: transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when uptf is 1, transfers bits 9, 8 to the low- order 2 bits (dr 1 , dr 0 ) of register d, and ?0? is stored to the least significant bit (dr 2 ) of register d. when this instruction is executed, 1 st age of stack register (sk) is used. note: m34571g4 : p = 0 to 31 m34571g6 : p = 0 to 47 m34571gd : p = 0 to 127 when this instruction is executed, be ca reful not to over the stack because 1 stage of stack register is used. tabps (transfer data to accumulator and register b from prescaler) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001110101 2 275 16 11 - - opera- tion: (b) (tps 7 ? tps 4 ) (a) (tps 3 ? tps 0 ) grouping: timer operation description: transfers the high-order 4 bits of prescaler to register b. transfers the low-order 4 bits of prescaler to register a.
rev.1.02 may 25, 2007 page 90 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tad (transfer data to accumulator from register d) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010001 2 051 16 11 - - opera- tion: (a 2 ? a 0 ) (dr 2 ? dr 0 ) (a 3 ) 0 grouping: register to register transfer description: transfers the contents of register d to the low-order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. tai1 (transfer data to accumulator from register i1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010011 2 253 16 11 - - opera- tion: (a) (i1) grouping: interrupt operation description: transfers the contents of interrupt control register i1 to register a. tai2 (transfer data to accumulator from register i2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010100 2 254 16 11 - - opera- tion: (a) (i2) grouping: interrupt operation description: transfers the contents of interrupt control register i2 to register a. tak0 (transfer data to accumu lator from register k0) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010110 2 256 16 11 - - opera- tion: (a) (k0) grouping: input/output operation description: transfers the contents of key-on wakeup control register k0 to register a.
rev.1.02 may 25, 2007 page 91 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tak1 (transfer data to accumu lator from register k1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011001 2 259 16 11 - - opera- tion: (a) (k1) grouping: input/output operation description: transfers the contents of key-on wakeup control register k1 to register a. tak2 (transfer data to accumu lator from register k2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011010 2 25a 16 11 - - opera- tion: (a) (k2) grouping: input/output operation description: transfers the contents of key-on wakeup control register k2 to register a. tal1 (transfer data to accumulator from register l1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001010 2 24a 16 11 - - opera- tion: (a) (l1) grouping: input/output operation description: transfers the contents of key-on wakeup control register l1 to register a. tam j (transfer data to accumulator from memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101100 j j j j 2 2c j 16 11 - - opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 grouping: ram to register transfer description: after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x.
rev.1.02 may 25, 2007 page 92 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tamr (transfer data to accumulator from register mr) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010010 2 252 16 11 - - opera- tion: (a) (mr) grouping: clock operation description: transfers the contents of clock control register mr to reg- ister a. tapu0 (transfer data to accumu lator from register pu0) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010111 2 257 16 11 - - opera- tion: (a) (pu0) grouping: input/output operation description: transfers the contents of pull-up control register pu0 to register a. tapu1 (transfer data to accumu lator from register pu1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011110 2 25e 16 11 - - opera- tion: (a) (pu1) grouping: input/output operation description: transfers the contents of pull-up control register pu1 to register a. tapu2 (transfer data to accumu lator from register pu2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011111 2 25f 16 11 - - opera- tion: (a) (pu2) grouping: input/output operation description: transfers the contents of pull-up control register pu2 to register a.
rev.1.02 may 25, 2007 page 93 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tasp (transfer data to accumulator from stack pointer) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010000 2 050 16 11 - - opera- tion: (a 2 ? a 0 ) (sp 2 ? sp 0 ) (a 3 ) 0 grouping: register to register transfer description: transfers the contents of stack pointer (sp) to the low- order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. tav1 (transfer data to accumulator from register v1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010100 2 054 16 11 - - opera- tion: (a) (v1) grouping: interrupt operation description: transfers the contents of interrupt control register v1 to register a. tav2 (transfer data to accumulator from register v2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010101 2 055 16 11 - - opera- tion: (a) (v2) grouping: interrupt operation description: transfers the contents of interrupt control register v2 to register a. taw1 (transfer data to accumu lator from register w1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001011 2 24b 16 11 - - opera- tion: (a) (w1) grouping: timer operation description: transfers the contents of timer control register w1 to regis- ter a.
rev.1.02 may 25, 2007 page 94 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) taw2 (transfer data to accumu lator from register w2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001100 2 24c 16 11 - - opera- tion: (a) (w2) grouping: timer operation description: transfers the contents of timer control register w2 to regis- ter a. taw3 (transfer data to accumu lator from register w3) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001101 2 24d 16 11 - - opera- tion: (a) (w3) grouping: timer operation description: transfers the contents of timer control register w3 to regis- ter a. taw5 (transfer data to accumu lator from register w5) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001111 2 24f 16 11 - - opera- tion: (a) (w5) grouping: timer operation description: transfers the contents of timer control register w5 to regis- ter a. tax (transfer data to accumulator from register x) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010010 2 052 16 11 - - opera- tion: (a) (x) grouping: register to register transfer description: transfers the contents of register x to register a.
rev.1.02 may 25, 2007 page 95 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tay (transfer data to accumulator from register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011111 2 01f 16 11 - - opera- tion: (a) (y) grouping: register to register transfer description: transfers the contents of register y to register a. taz (transfer data to accumulator from register z) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010011 2 053 16 11 - - opera- tion: (a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 grouping: register to register transfer description: transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. tba (transfer data to register b from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001110 2 00e 16 11 - - opera- tion: (b) (a) grouping: register to register transfer description: transfers the contents of register a to register b. tda (transfer data to register d from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000101001 2 029 16 11 - - opera- tion: (dr 2 ? dr 0 ) (a 2 ? a 0 ) grouping: register to register transfer description: transfers the contents of the low-order 3 bits (a 2 ? a 0 ) of register a to register d.
rev.1.02 may 25, 2007 page 96 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) teab (transfer data to register e from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011010 2 01a 16 11 - - opera- tion: (e 7 ? e 4 ) (b) (e 3 ? e 0 ) (a) grouping: register to register transfer description: transfers the contents of register b to the high-order 4 bits (e 3 ? e 0 ) of register e, and the contents of register a to the low-order 4 bits (e 3 ? e 0 ) of register e. tfr0a (transfer data to register fr0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101000 2 228 16 11 - - opera- tion: (fr0) (a) grouping: input/output operation description: transfers the contents of register a to port output structure control register fr0. tfr1a (transfer data to register fr1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101001 2 229 16 11 - - opera- tion: (fr1) (a) grouping: input/output operation description: transfers the contents of register a to port output structure control register fr1. ti1a (transfer data to register i1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010111 2 217 16 11 - - opera- tion: (i1) (a) grouping: interrupt operation description: transfers the contents of register a to interrupt control reg- ister i1.
rev.1.02 may 25, 2007 page 97 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) ti2a (transfer data to register i2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000011000 2 218 16 11 - - opera- tion: (i2) (a) grouping: interrupt operation description: transfers the contents of register a to interrupt control reg- ister i2. tk0a (transfer data to register k0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000011011 2 21b 16 11 - - opera- tion: (k0) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register k0. tk1a (transfer data to register k1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010100 2 214 16 11 - - opera- tion: (k1) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register k1. tk2a (transfer data to register k2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010101 2 215 16 11 - - opera- tion: (k2) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register k2.
rev.1.02 may 25, 2007 page 98 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tl1a (transfer data to register l1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001010 2 20a 16 11 - - opera- tion: (l1) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register l1. tma j (transfer data to memory from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101011 j j j j 2 2b j 16 11 - - opera- tion: (m(dp)) (a) (x) (x)exor(j) j = 0 to 15 grouping: ram to register transfer description: after transferring the contents of register a to m(dp), an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. tmra (transfer data to register mr from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010110 2 216 16 11 - - opera- tion: (mr) (a) grouping: clock operation description: transfers the contents of register a to clock control regis- ter mr. tpaa (transfer data to register pa from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010101010 2 2aa 16 11 - - opera- tion: (pa 0 ) (a 0 ) grouping: timer operation description: transfers the least si gnificant bit of register a (a 0 ) to timer control register pa.
rev.1.02 may 25, 2007 page 99 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tpsab (transfer data to prescaler and register rps from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110101 2 235 16 11 - - opera- tion: (rps 7 ? rps 4 ) (b) (tps 7 ? tps 4 ) (b) (rps 3 ? rps 0 ) (a) (tps 3 ? tps 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps. transfers the contents of register a to the low-order 4 bits of pres- caler and prescaler reload register rps. tpu0a (transfer data to register pu0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101101 2 22d 16 11 - - opera- tion: (pu0) (a) grouping: input/output operation description: transfers the contents of register a to pull-up control regis- ter pu0. tpu1a (transfer data to register pu1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101110 2 22e 16 11 - - opera- tion: (pu1) (a) grouping: input/output operation description: transfers the contents of register a to pull-up control regis- ter pu1. tpu2a (transfer data to register pu2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101111 2 22f 16 11 - - opera- tion: (pu2) (a) grouping: input/output operation description: transfers the contents of register a to pull-up control regis- ter pu2.
rev.1.02 may 25, 2007 page 100 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tr1ab (transfer data to register r1 from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000111111 2 23f 16 11 - - opera- tion: (r1 7 ? r1 4 ) (b) (r1 3 ? r1 0 ) (a) grouping: input/output operation description: transfers the contents of register b to the high-order 4 bits (r1 7 ? r1 4 ) of reload register r1, and the contents of regis- ter a to the low-order 4 bits (r1 3 ? r1 0 ) of reload register r1. tv1a (transfer data to register v1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111111 2 03f 16 11 - - opera- tion: (v1) (a) grouping: interrupt operation description: transfers the contents of register a to interrupt control reg- ister v1. tv2a (transfer data to register v2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111110 2 03e 16 11 - - opera- tion: (v2) (a) grouping: interrupt operation description: transfers the contents of register a to interrupt control reg- ister v2. tw1a (transfer data to register w1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001110 2 20e 16 11 - - opera- tion: (w1) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w1.
rev.1.02 may 25, 2007 page 101 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) tw2a (transfer data to register w2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001111 2 20f 16 11 - - opera- tion: (w2) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w2. tw3a (transfer data to register w3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010000 2 210 16 11 - - opera- tion: (w3) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w3. tw5a (transfer data to register w5 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010010 2 212 16 11 - - opera- tion: (w5) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w5. tya (transfer data to register y from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001100 2 00c 16 11 - - opera- tion: (y) (a) grouping: register to register transfer description: transfers the contents of register a to register y.
rev.1.02 may 25, 2007 page 102 of 124 rej03b0179-0102 4571 group machine instructions (index by alphabet) (continued) wrst (watchdog timer reset) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010100000 2 2a0 16 11 - (wdf1) = 1 opera- tion: (wdf1) = 1 ? (wdf1) 0 grouping: other operation description: clears (0) to the wdf1 flag and skips the next instruction when watchdog timer flag wdf1 is ?1?. when the wdf1 flag is ?0?, executes the next instruction. also, stops the watchdog timer function when executing the wrst instruction immediately after the dwdt instruction. xam j (exchange accumulator and memory data) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101101 j j j j 2 2d j 16 11 - - opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 grouping: ram to register transfer description: after exchanging the cont ents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the val ue j in the immediate field, and stores the result in register x. xamd j (exchange accumulator and memory data and decrement register y and skip) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101111 j j j j 2 2f j 16 11 - (y) = 15 opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ? 1 grouping: ram to register transfer description: after exchanging the cont ents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the val ue j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. xami j (exchange accumulator and memory data and increment register y and skip) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101110 j j j j 2 2e j 16 11 - (y) = 0 opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 grouping: ram to register transfer description: after exchanging the cont ents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the val ue j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of r egister y is not 0, the next instruction is executed.
rev.1.02 may 25, 2007 page 103 of 124 rej03b0179-0102 4571 group machine instructions (index by types) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation register to register transfer tab 000001111001e 1 1(a) (b) tba 000000111000e 1 1(b) (a) tay 000001111101f 1 1(a) (y) tya 000000110000c 1 1(y) (a) teab 000001101001a 1 1(e 7 ? e 4 ) (b) (e 3 ? e 0 ) (a) tabe 000010101002a 1 1(b) (e 7 ? e 4 ) (a) (e 3 ? e 0 ) tda 0000101001029 1 1(dr 2 ? dr 0 ) (a 2 ? a 0 ) tad 0001010001051 1 1(a 2 ? a 0 ) (dr 2 ? dr 0 ) (a 3 ) 0 taz 0001010011053 1 1(a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 tax 0001010010052 1 1(a) (x) tasp 0001010000050 1 1(a 2 ? a 0 ) (sp 2 ? sp 0 ) (a 3 ) 0 ram addresses lxy x, y 1 1 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 3xy 1 1(x) x x = 0 to 15 (y) y y = 0 to 15 lz z 00010010z 1 z 0 048 +z 1 1 (z) z z = 0 to 3 iny 0000010011013 1 1(y) (y) + 1 dey 0000010111017 1 1(y) (y) ? 1 ram to register transfer tam j 101100 j j j j 2cj 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 xam j 101101 j j j j 2dj 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 xamd j 101111 j j j j 2f j 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ? 1 xami j 101110 j j j j 2e j 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 tma j 101011 j j j j 2b j 1 1(m(dp)) (a) (x) (x)exor(j) j = 0 to 15 para meter type of instructi ons
rev.1.02 may 25, 2007 page 104 of 124 rej03b0179-0102 4571 group skip condition carry flag cy detailed description ?? transfers the contents of register b to register a. ?? transfers the contents of register a to register b. ?? transfers the contents of register y to register a. ?? transfers the contents of register a to register y. ?? transfers the contents of register b to the high-order 4 bits (e 3 ? e 0 ) of register e, and the contents of register a to the low-order 4 bits (e 3 ? e 0 ) of register e. ?? transfers the high-order 4 bits (e 7 ? e 4 ) of register e to register b, and low- order 4 bits of register e to register a. ?? transfers the contents of the low-order 3 bits (a 2 ? a 0 ) of register a to register d. ?? transfers the contents of register d to the low-order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. ?? transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. ?? transfers the contents of register x to register a. ?? transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. continuous description ? loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are cont inuously coded and executed, only the first lxy instruction is executed and other lxy instructions c oded continuously are skipped. ?? loads the value z in the immediate field to register z. (y) = 0 ? adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. (y) = 15 ? subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of regi ster y is not 15, the nex t instruction is executed. ?? after transferring the contents of m(dp) to regist er a, an exclusive or operation is performed between register x and the value j in the immediate fi eld, and stores the result in register x. ?? after exchanging the contents of m(dp ) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immed iate field, and stores the result in register x. (y) = 15 ? after exchanging the contents of m(dp ) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immed iate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of regi ster y is not 15, the nex t instruction is executed. (y) = 0 ? after exchanging the contents of m(dp ) with the contents of register a, an exclusive or operation is performed between register x and the value j in the immed iate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the c ontents of register y is not 0, the next instruction is executed. ?? after transferring the contents of register a to m(dp), an exclusive or operation is performed between register x and the value j in the immediate fi eld, and stores the result in register x.
rev.1.02 may 25, 2007 page 105 of 124 rej03b0179-0102 4571 group note 1.m34571g4: p=0 to 31, m34571g6: p=0 to 47 and m34571gd: p=0 to 127. machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation arithmetic operation la n 000111nnnn07n 1 1(a) n n = 0 to 15 tabp p 0010p 5 p 4 p 3 p 2 p 1 p 0 08 +p p 1 3 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note 1) (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) (b) (rom(pc)) 7 - 4 (a) (rom(pc)) 3 - 0 (uptf) = 1 (dr 1 , dr 0 ) (rom(pc)) 9 , 8 (dr 2 ) 0 (pc) (sk(sp)) (sp) (sp) ? 1 am 000000101000a 1 1(a) (a) + (m(dp)) amc 000000101100b 1 1(a) (a) + (m(dp)) + (cy) (cy) carry a n 000110nnnn06n 1 1(a) (a) + n n = 0 to 15 and 0000011000018 1 1(a) (a) and (m(dp)) or 0000011001019 1 1(a) (a) or (m(dp)) sc 0000000111007 1 1(cy) 1 rc 0000000110006 1 1(cy) 0 szc 000010111102f 1 1(cy) = 0 ? cma 000001110001c 1 1(a) (a) rar 000001110101d 1 1 bit operation sb j 00010111 j j 05c +j 1 1 (mj(dp)) 1 j = 0 to 3 rb j 00010011 j j 04c +j 1 1 (mj(dp)) 0 j = 0 to 3 szb j 00001000 j j 02 j 1 1(mj(dp)) = 0 ? j = 0 to 3 para meter type of instructi ons cy a 3 a 2 a 1 a 0
rev.1.02 may 25, 2007 page 106 of 124 rej03b0179-0102 4571 group skip condition carry flag cy detailed description continuous description ? loads the value n in the immedi ate field to register a. when the la instructions are continuously coded and ex ecuted, only the first la instruction is executed and other la instructions c oded continuously are skipped. ?? transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in p age p. when uptf is 1, transfers bits 9, 8 to the low-order 2 bits (dr 1 , dr 0 ) of register d, and ?0? is stored to the least si gnificant bit (dr 2 ) of register d. when this instruction is executed, 1 stage of stack register (sk) is used. ?? adds the contents of m(dp) to register a. stores t he result in register a. the contents of carry flag cy remains unchanged. ? 0/1 adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. overflow = 0 ? adds the value n in the immediate field to regi ster a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instructi on when there is overflow as the result of operation. ?? takes the and operation between the contents of register a and the contents of m(dp), and stores the result in register a. ?? takes the or operation between the contents of regist er a and the contents of m(dp), and stores the result in register a. ? 1 sets (1) to carry flag cy. ? 0 clears (0) to carry flag cy. (cy) = 0 ? skips the next instruction when the contents of carry fl ag cy is ?0?. executes t he next instruction when the contents of carry flag cy is ?1?. the contents of carry flag cy remains unchanged. ?? stores the one?s complement for register a?s contents in register a. ? 0/1 rotates 1 bit of the contents of register a including the content s of carry flag cy to the right. ?? sets (1) the contents of bit j (bit specified by the value j in the i mmediate field) of m(dp). ?? clears (0) the contents of bit j (bit specified by the value j in the i mmediate field) of m(dp). (mj(dp)) = 0 j = 0 to 3 ? skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is ?0?. executes the next instruction when the contents of bit j of m(dp) is ?1?.
rev.1.02 may 25, 2007 page 107 of 124 rej03b0179-0102 4571 group note 1.m34571g4: p=0 to 31, m34571g6: p=0 to 47 and m34571gd: p=0 to 127. machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation comparison operation seam 0000100110026 1 1(a) = (m(dp)) ? sea n 0000100101025 2 2(a) = n n = 0 to 15 000111nnnn07n branch operation b a 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 18 +a a1 1(pc l ) a 6 ? a 0 bl p, a 00111p 4 p 3 p 2 p 1 p 0 0e +p p2 2(pc h ) p (note 1) (pc l ) a 6 ? a 0 1p 6 p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2aa bla p 0000010000 010 2 2(pc h ) p (note 1) (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 2pp subroutine operation bm a 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa 1 1(sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? a 0 bml p, a 00110p 4 p 3 p 2 p 1 p 0 0c +p p 2 2 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note 1) (pc l ) a 6 ? a 0 1p 6 p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2aa bmla p 0000110000 030 2 2(sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note 1) (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 1p 6 p 5 p 4 00p 3 p 2 p 1 p 0 2pp return operation rti 0001000110046 1 1(pc) (sk(sp)) (sp) (sp) ? 1 rt 0001000100044 1 2(pc) (sk(sp)) (sp) (sp) ? 1 rts 0001000101045 1 2(pc) (sk(sp)) (sp) (sp) ? 1 para meter type of instructi ons
rev.1.02 may 25, 2007 page 108 of 124 rej03b0179-0102 4571 group skip condition carry flag cy detailed description (a) = (m(dp)) ? skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of register a is not equal to the contents of m(dp). (a) = n n = 0 to 15 ? skips the next instruction when the contents of regist er a is equal to the value n in the immediate field. executes the next instruction when t he contents of register a is not equal to the value n in the immediate field. ?? branch within a page : branches to address a in the identical page. ?? branch out of a page : branches to address a in page p. ?? branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. ?? call the subroutine in page 2 : calls the subroutine at address a in page 2. ?? call the subroutine : calls the subroutine at address a in page p. ?? call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. ?? returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy instruction, register a and register b to the states just before interrupt. ?? returns from subroutine to the routine called the subroutine. no conditional skip ? returns from subroutine to the routine called the subr outine, and skips the next instruction at with no condition.
rev.1.02 may 25, 2007 page 109 of 124 rej03b0179-0102 4571 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation interrupt operation di 0000000100004 1 1(inte) 0 ei 0000000101005 1 1(inte) 1 snz0 0 000111000038 1 1v1 0 = 0 : (exf0) = 1 ? (exf0) 0 v1 0 = 1 : snz0 = nop snzi0 000011101003a 1 1i1 2 = 0 : (int0) = ?l?? i1 2 = 1 : (int0) = ?h?? snz1 0 000111001039 1 1v1 1 = 0 : (exf1) = 1 ? (exf1) 0 v1 1 = 1 : snz1 = nop snzi1 000011101103b 1 1i2 2 = 0 : (int1) = ?l? ? i2 2 = 1 : (int1) = ?h? ? tav1 0001010100054 1 1(a) (v1) tv1a 000011111103f 1 1(v1) (a) tav2 0001010101055 1 1(a) (v2) tv2a 000011111003e 1 1(v2) (a) tai1 1001010011253 1 1(a) (i1) ti1a 1000010111217 1 1(i1) (a) tai2 1001010100254 1 1(a) (i2) ti2a 1000011000218 1 1(i2) (a) timer operation tpaa 10101010102aa 1 1(pa 1, pa 0 ) (a 1, a 0 ) taw1 100100101124b 1 1(a) (w1) tw1a 100000111020e 1 1(w1) (a) taw2 100100110024c 1 1(a) (w2) tw2a 100000111120f 1 1(w2) (a) taw3 100100110124d 1 1(a) (w3) tw3a 1000010000210 1 1(w3) (a) taw5 100100111124f 1 1(a) (w5) tw5a 1000010010212 1 1(w5) (a) para meter type of instructi ons
rev.1.02 may 25, 2007 page 110 of 124 rej03b0179-0102 4571 group skip condition carry flag cy detailed description ?? clears (0) to interrupt enable flag inte, and disables the interrupt. ?? sets (1) to interrupt enable flag inte, and enables the interrupt. v1 0 = 0 : (exf0) = 1 ? when v1 0 = 0 : clears (0) to the exf0 flag and skips the next instruction when external 0 interrupt request flag exf0 is ?1?. when the exf0 flag is ?0?, executes the next instruction. when v1 0 = 1 : this instruction is equival ent to the nop instruction. (v1 0 : bit 0 of interrupt control register v1) (int0) = ? l ? however, i1 2 = 0 ? when i1 2 = 0 : skips the next instruction when the level of in t0 pin is ?l?. executes the next instruction when the level of int0 pin is ?h?. (int0) = ? h ? however, i1 2 = 1 when i1 2 = 1 : skips the next instruction when the level of in t0 pin is ?h?. executes the next instruction when the level of int0 pin is ?l?. (i1 2 : bit 2 of interrupt control register i1) v1 1 = 0 : (exf1) = 1 ? when v1 1 = 0 : clears (0) to the exf1 flag and skips the nex t instruction when external 1 interrupt request flag exf1 is ?1?. when the exf1 flag is ?0?, executes the next instruction. when v1 1 = 1 : this instruction is equivalent to the nop instruction. (v1 1 : bit 1 of interrupt control register v1) i2 2 = 0 : (int1) = ? l ? ? when i2 2 = 0 : skips the next instruction when the level of in t1 pin is ?l?. executes the next instruction when the level of int1 pin is ?h?. i2 2 = 1 : (int1) = ? h ? when i2 2 = 1 : skips the next instruction when the level of in t1 pin is ?h?. executes the next instruction when the level of int1 pin is ?l?. (i2 2 : bit 2 of interrupt control register i2) ?? transfers the contents of interrupt control register v1 to register a. ?? transfers the contents of register a to interrupt control register v1. ?? transfers the contents of interrupt control register v2 to register a. ?? transfers the contents of register a to interrupt control register v2. ?? transfers the contents of interrupt control register i1 to register a. ?? transfers the contents of register a to interrupt control register i1. ?? transfers the contents of interrupt control register i2 to register a. ?? transfers the contents of register a to interrupt control register i2. ?? transfers the contents of register a (a 1 , a 0 ) to timer control register pa. ?? transfers the contents of timer control register w1 to register a. ?? transfers the contents of register a to timer control register w1. ?? transfers the contents of timer control register w2 to register a. ?? transfers the contents of register a to timer control register w2. ?? transfers the contents of timer control register w3 to register a. ?? transfers the contents of register a to timer control register w3. ?? transfers the contents of timer control register w5 to register a. ?? transfers the contents of register a to timer control register w5.
rev.1.02 may 25, 2007 page 111 of 124 rej03b0179-0102 4571 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation timer operation tabps 1001110101275 1 1(b) (tps 7 ? tps 4 ) (a) (tps 3 ? tps 0 ) tpsab 1000110101235 1 1(rps 7 ? rps 4 ) (b) (tps 7 ? tps 4 ) (b) (rps 3 ? rps 0 ) (a) (tps 3 ? tps 0 ) (a) tab1 1001110000270 1 1(b) (t1 7 ? t1 4 ) (a) (t1 3 ? t1 0 ) t1ab 1000110000230 1 1(r1 7 ? r1 4 ) (b) (t1 7 ? t1 4 ) (b) (r1 3 ? r1 0 ) (a) (t1 3 ? t1 0 ) (a) tr1ab 100011111123f 1 1(r1 7 ? r1 4 ) (b) (r1 3 ? r1 0 ) (a) tab2 1001110001271 1 1(b) (t2 7 ? t2 4 ) (a) (t2 3 ? t2 0 ) t2ab 1000110001231 1 1(r2 7 ? r2 4 ) (b) (t2 7 ? t2 4 ) (b) (r2 3 ? r2 0 ) (a) (t2 3 ? t2 0 ) (a) tab3 1001110010272 1 1(b) (t3 7 ? t3 4 ) (a) (t3 3 ? t3 0 ) t3ab 1000110010232 1 1(r3l 7 ? r3l 4 ) (b) (t3 7 ? t3 4 ) (b) (r3l 3 ? r3l 0 ) (a) (t3 3 ? t3 0 ) (a) t3hab 100011110123d 1 1(r3h 7 ? r3h 4 ) (b) (r3h 3 ? r3h 0 ) (a) t3r3l 1000110100234 1 1(t3 7 ) (r3l) snzt1 1010000000280 1 1v1 2 = 0 : (t1f) = 1 ? after skipping, (t1f) 0 v1 2 = 1 : snzt1=nop snzt2 1010000001281 1 1v1 3 = 0 : (t2f) = 1 ? after skipping, (t2f) 0 v1 3 = 1 : snzt2=nop snzt3 1010000010282 1 1v2 0 = 0 : (t3f) = 1 ? after skipping, (t3f) 0 v2 0 = 1 : snzt3=nop para meter type of instructi ons
rev.1.02 may 25, 2007 page 112 of 124 rej03b0179-0102 4571 group skip condition carry flag cy detailed description ?? transfers the high-order 4 bits of prescaler to register b. transfers the low-order 4 bits of prescaler to register a. ?? transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps. transfers the contents of register a to the low-order 4 bits of prescaler and prescaler reload register rps. ?? transfers the high-order 4 bits (t1 7 ? t1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 ? t1 0 ) of timer 1 to register a. ?? transfers the contents of register b to the high-orde r 4 bits of timer 1 and timer 1 reload register r1l. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1l. ?? transfers the contents of register b to the high-order 4 bits (r1 7 ? r1 4 ) of reload register r1, and the contents of register a to the low-order 4 bits (r1 3 ? r1 0 ) of reload register r1. ?? transfers the high-order 4 bits (t2 7 ? t2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 ? t2 0 ) of timer 2 to register a. ?? transfers the contents of register b to the high-orde r 4 bits of timer 2 and timer 2 reload register r2l. transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2l. ?? transfers the high-order 4 bits (t3 7 ? t3 4 ) of timer 3 to register b. transfers the low-order 4 bits (t3 3 ? t3 0 ) of timer 3 to register a. ?? transfers the contents of register b to the high-orde r 4 bits of timer 3 and timer 3 reload register r3l. transfers the contents of register a to the low-order 4 bits of timer 3 and timer 3 reload register r3l. ?? transfers the contents of register b to the high- order 4 bits of timer 3 reload register r3h. transfers the contents of register a to the low- order 4 bits of timer 3 reload register r3h. ?? transfers the contents of timer 3 reload register r3l to timer 3. v1 2 = 0 : (t1f) = 1 ? when v1 2 = 0 : clears (0) to the t1f flag and skips the next instruction when timer 1 interrupt request flag t1f is ?1?. when the t1f flag is ?0 ?, executes the next instruction. when v1 2 = 1 : this instruction is equiva lent to the nop instruction. (v1 2 : bit 2 of interrupt control register v1) v1 3 = 0 : (t2f) = 1 ? when v1 3 = 0 : clears (0) to the t2f flag and skips the next instruction when timer 2 interrupt request flag t2f is ?1?. when the t2f flag is ?0 ?, executes the next instruction. when v1 3 = 1 : this instruction is equiva lent to the nop instruction. (v1 3 : bit 3 of interrupt control register v1) v2 0 = 0 : (t3f) = 1 ? when v2 0 = 0 : clears (0) to the t3f flag and skips the next instruction when timer 3 interrupt request flag t3f is ?1?. when the t3f flag is ?0 ?, executes the next instruction. when v2 0 = 1 : this instruction is equiva lent to the nop instruction. (v2 0 : bit 0 of interrupt control register v2)
rev.1.02 may 25, 2007 page 113 of 124 rej03b0179-0102 4571 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation input/output operation iap0 1001100000260 1 1(a) (p0) op0a 1000100000220 1 1(p0) (a) iap1 1001100001261 1 1(a) (p1) op1a 1000100001221 1 1(p1) (a) iap2 1001100010262 1 1(a 1 , a 0 ) (p2 1 , p2 0 ) (a 3 , a 2 ) 0 op2a 1000100010222 1 1(p2 1 , p2 0 ) (a 1 , a 0 ) iap3 1001100011263 1 1(a 1 , a 0 ) (p3 1 , p3 0 ) (a 3 , a 2 ) 0 op3a 1000100011223 1 1(p3 1 , p3 0 ) (a 1 , a 0 ) cld 0000010001011 1 1(d) 1 rd 0000010100014 1 1(d(y)) 0 (y) = 0 to 4 sd 0000010101015 1 1(d(y)) 1 (y) = 0 to 4 szd 0000100100024 2 2(d(y)) = 0 ? (y) = 0 to 4 000010101102b rcp 101000110028c 1 1(c) (0) scp 101000110128d 1 1(c) (1) tfr0a 1000101000228 1 1(fr0) (a) tfr1a 1000101001229 1 1(fr1) (a) tapu0 1001010111257 1 1(a) (pu0) tpu0a 100010110122d 1 1(pu0) (a) tapu1 100101111025e 1 1(a) (pu1) tpu1a 100010111022e 1 1(pu1) (a) tapu2 100101111125f 1 1(a) (pu2) tpu2a 100010111122f 1 1(pu2) (a) iak 100110111126f 1 1(a 0 ) (k) (a 3 ? a 1 ) 0 para meter type of instructi ons
rev.1.02 may 25, 2007 page 114 of 124 rej03b0179-0102 4571 group skip condition carry flag cy detailed description ?? transfers the input of port p0 to register a. ?? outputs the contents of register a to port p0. ?? transfers the input of port p1 to register a. ?? outputs the contents of register a to port p1. ?? transfers the input of port p2 to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. ?? outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p2. ?? transfers the input of port p3 to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. ?? outputs the contents of the low-order 2 bits (a 1 , a 0 ) of register a to port p3. ?? sets (1) to port d. ?? clears (0) to a bit of port d specified by register y. ?? sets (1) to a bit of port d specified by register y. (d(y)) = 0 y = 0 to 4 ? skips the next instruction when a bit of port d specified by register y is ?0?. executes the next instruction when a bit of port d specifi ed by register y is ?1?. ?? clears (0) to port c. ?? sets (1) to port c. ?? transfers the contents of register a to port output structure control register fr0. ?? transfers the contents of register a to port output structure control register fr1. ?? transfers the contents of pull-up control register pu0 to register a. ?? transfers the contents of register a to pull-up control register pu0. ?? transfers the contents of pull-up control register pu1 to register a. ?? transfers the contents of register a to pull-up control register pu1. ?? transfers the contents of pull-up control register pu2 to register a. ?? transfers the contents of register a to pull-up control register pu2. ?? transfers the input of port k to the least significant bit (a 0 ) of register a. ?0? is stored to the high-order 3 bits (a 3 ? a 1 ) of register a.
rev.1.02 may 25, 2007 page 115 of 124 rej03b0179-0102 4571 group note 1.this instruction c annot be used for the m34571g4/g6. machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation input/output operation tak0 1001010110256 1 1(a) (k0) tk0a 100001101121b 1 1(k0) (a) tak1 1001011001259 1 1(a) (k1) tk1a 1000010100214 1 1(k1) (a) tak2 100101101025a 1 1(a) (k2) tk2a 1000010101215 1 1(k2) (a) tal1 100100101024a 1 1(a) (l1) tl1a 100000101020a 1 1(l1) (a) other operation tamr 1001010010252 1 1(a) (mr) tmra 1000010110216 1 1(mr) (a) nop 0000000000000 1 1(pc) (pc) + 1 pof 0000000010002 1 1ram back-up epof 000101101105b 1 1pof instruction valid snzp 0000000011003 1 1(p) = 1 ? wrst 10101000002a0 1 1(wdf1) = 1 ? (wdf1) 0 dwdt 101001110029c 1 1stop of watc hdog timer function enabled srst 0000000001001 1 1system reset rupt 0001011000058 1 1(uptf) 0 supt 0001011001059 1 1(uptf) 1 snzvd 101000101028a 1 1v2 3 = 0 : (vdf) = 1? v2 3 = 1 : snzvd = nop rbk (note 1) 0001000000040 1 1p 6 0 when tabp p instruction is executed. sbk (note 1) 0001000001041 1 1p 6 1 when tabp p instruction is executed. para meter type of instructi ons
rev.1.02 may 25, 2007 page 116 of 124 rej03b0179-0102 4571 group skip condition carry flag cy detailed description ?? transfers the contents of key-on wakeup control register k0 to register a. ?? transfers the contents of register a to key-on wakeup control register k0. ?? transfers the contents of key-on wakeup control register k1 to register a. ?? transfers the contents of register a to key-on wakeup control register k1. ?? transfers the contents of key-on wakeup control register k2 to register a. ?? transfers the contents of register a to key-on wakeup control register k2. ?? transfers the contents of key-on wakeup control register l1 to register a. ?? transfers the contents of register a to key-on wakeup control register l1. ?? transfers the contents of clock cont rol register mr to register a. ?? transfers the contents of register a to clock control register mr. ?? no operation; adds 1 to program c ounter value, and others remain unchanged. ?? puts the system in ram back-up state by execut ing the pof instruction after executing the epof instruction. operations of all functions are stopped. ?? makes the immediate after pof instruction valid by exec uting the epof instruction. (p) = 1 ? skips the next instruction when the p flag is ?1?. after skipping, the p flag remains unchanged. executes the next instruct ion when the p flag is ?0?. (wdf1) = 1 clears (0) to the wdf1 flag and skips the next instruction when watchdog timer flag wdf1 is ?1?. when the wdf1 flag is ?0?, executes the nex t instruction. also, stops the watc hdog timer function when executing the wrst instruction immediately after the dwdt instruction. ?? stops the watchdog timer function by the wrst in struction after executi ng the dwdt instruction. ?? system reset occurs. ?? clears (0) to the high-order bit reference enable flag uptf. ?? sets (1) to the high-order bit reference enable flag uptf. v2 3 = 0 : (vdf) = 1 ? when v2 3 = 0 : skips the next instruction when voltage detect or interrupt request flag vdf is ?1?. the vdf flag is not cleared to ?0?. when the vdf fl ag is ?0?, executes the next instruction. when v2 3 = 1 : this instruction is equi valent to the nop instruction. ?? sets referring data area to pages 0 to 63 when the tabp p instruction is executed. this instruction is valid only for the tabp p instruction. ?? sets referring data area to pages 64 to 127 when the tabp p instruction is executed. this instruction is valid only for the tabp p instruction.
rev.1.02 may 25, 2007 page 117 of 124 rej03b0179-0102 4571 group the above table shows the relations hip between machine language codes and machine language instructions. d 3? d 0 show the low-order 4 bits of the machine language code, and d 9? d 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is al so provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked ??.? the codes for the second word of a two-word instruction are described below. ? *, **, and *** cannot be used in the m34571g4. ? ** and *** cannot be used in the m34571g6. ? a page referred by the tabp instruction can be switched by the sbk and rbk instructions in the m34571gd. the pages which can be referred by the tabp instruction after the rbk instruction is executed are 0 to 63. the pages which can be referred by the tabp instruction after the sbk instruction is executed are 64 to 127 (ex. tabp 0 tabp 64). when the sbk instruction is not used, the pages which can be referred by the tabp instruction are 0 to 63. instruction code table d 9 ? d 4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 00 1111 010000 to 010111 011000 to 011111 d 3 ? d 0 hex, notation 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 ? 17 18 ? f 0000 0 nop bla szb 0 bmla rbk *** tasp a 0 la 0 tabp 0 tabp 16 tabp 32* tabp 48** bml bml bl bl bm b 0001 1 srst cld szb 1 ? sbk *** tad a 1 la 1 tabp 1 tabp 17 tabp 33* tabp 49** bml bml bl bl bm b 0010 2 pof ? szb 2 ?? tax a 2 la 2 tabp 2 tabp 18 tabp 34* tabp 50** bml bml bl bl bm b 0011 3 snzp iny szb 3 ?? taz a 3 la 3 tabp 3 tabp 19 tabp 35* tabp 51** bml bml bl bl bm b 0100 4 di rd szd ? rt tav1 a 4 la 4 tabp 4 tabp 20 tabp 36* tabp 52** bml bml bl bl bm b 0101 5 ei sd sean ? rts tav2 a 5 la 5 tabp 5 tabp 21 tabp 37* tabp 53** bml bml bl bl bm b 0110 6 rc ? seam ? rti ? a 6 la 6 tabp 6 tabp 22 tabp 38* tabp 54** bml bml bl bl bm b 0111 7 sc dey ???? a 7 la 7 tabp 7 tabp 23 tabp 39* tabp 55** bml bml bl bl bm b 1000 8 ? and ? snz0 lz 0 rupt a 8 la 8 tabp 8 tabp 24 tabp 40* tabp 56** bml bml bl bl bm b 1001 9 ? or tda snz1 lz 1 supt a 9 la 9 tabp 9 tabp 25 tabp 41* tabp 57** bml bml bl bl bm b 1010 a am teab tabe snzi 0 lz 2 ? a 10 la 10 tabp 10 tabp 26 tabp 42* tabp 58** bml bml bl bl bm b 1011 b amc ?? snzi 1 lz 3 epof a 11 la 11 tabp 11 tabp 27 tabp 43* tabp 59** bml bml bl bl bm b 1100 c tya cma ?? rb 0 sb 0 a 12 la 12 tabp 12 tabp 28 tabp 44* tabp 60** bml bml bl bl bm b 1101 d ? rar ?? rb 1 sb 1 a 13 la 13 tabp 13 tabp 29 tabp 45* tabp 61** bml bml bl bl bm b 1110 e tba tab ? tv2a rb 2 sb 2 a 14 la 14 tabp 14 tabp 30 tabp 46* tabp 62** bml bml bl bl bm b 1111 f ? tay szc tv1a rb 3 sb 3 a 15 la 15 tabp 15 tabp 31 tabp 47* tabp 63** bml bml bl bl bm b the second word bl 10 0aaa aaaa bml 10 0aaa aaaa bla 10 0p00 pppp bmla 10 0p00 pppp sea 00 0111 nnnn szd 00 0010 1011
rev.1.02 may 25, 2007 page 118 of 124 rej03b0179-0102 4571 group the above table shows the relations hip between machine language codes and machine language instructions. d 3? d 0 show the low-order 4 bits of the machine language code, and d 9? d 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is al so provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked ??.? the codes for the second word of a two-word instruction are described below. instruction code table d 9 ? d 4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 10 1111 110000 to 111111 d 3 ? d 0 hex, notation 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 ? 3f 0000 0 ? tw3a op0a t1ab ?? iap0 tab1 snzt 1 ? wrst tma 0 tam 0 xam 0 xami 0 xamd 0 lxy 0001 1 ?? op1a t2ab ?? iap1 tab2 snzt 2 ?? tma 1 tam 1 xam 1 xami 1 xamd 1 lxy 0010 2 ? tw5a op2a t3ab ? tamr iap2 tab3 snzt 3 ?? tma 2 tam 2 xam 2 xami 2 xamd 2 lxy 0011 3 ?? op3a ?? tai1 iap3 ???? tma 3 tam 3 xam 3 xami 3 xamd 3 lxy 0100 4 ? tk1a ? t3r3l ? tai2 ????? tma 4 tam 4 xam 4 xami 4 xamd 4 lxy 0101 5 ? tk2a ? tpsab ??? tabps ??? tma 5 tam 5 xam 5 xami 5 xamd 5 lxy 0110 6 ? tmra ??? tak0 ????? tma 6 tam 6 xam 6 xami 6 xamd 6 lxy 0111 7 ? ti1a ??? tapu0 ????? tma 7 tam 7 xam 7 xami 7 xamd 7 lxy 1000 8 ? ti2a tfr0a ???????? tma 8 tam 8 xam 8 xami 8 xamd 8 lxy 1001 9 ?? tfr1a ?? tak1 ????? tma 9 tam 9 xam 9 xami 9 xamd 9 lxy 1010 a tl1a ??? tal1 tak2 ?? snzvd ? tpaa tma 10 tam 10 xam 10 xami 10 xamd 10 lxy 1011 b ? tk0a ?? taw1 ?????? tma 11 tam 11 xam 11 xami 11 xamd 11 lxy 1100 c ???? taw2 ??? rcp dwdt ? tma 12 tam 12 xam 12 xami 12 xamd 12 lxy 1101 d ?? tpu0a t3hab taw3 ??? scp ?? tma 13 tam 13 xam 13 xami 13 xamd 13 lxy 1110 e tw1a ? tpu1a ?? tapu1 ????? tma 14 tam 14 xam 14 xami 14 xamd 14 lxy 1111 f tw2a ? tpu2a tr1ab taw5 tapu2 iak ???? tma 15 tam 15 xam 15 xami 15 xamd 15 lxy the second word bl 10 0aaa aaaa bml 10 0aaa aaaa bla 10 0p00 pppp bmla 10 0p00 pppp sea 00 0111 nnnn szd 00 0010 1011
rev.1.02 may 25, 2007 page 119 of 124 rej03b0179-0102 4571 group electrical characteristics absolute maximum ratings table 25 absolute maximum ratings symbol parameter conditions ratings unit v dd supply voltage - ? 0.3 to 6.5 v v i input voltage p0, p1, p2 0 /int0, p2 1 /int1, p3, d 0 ? d 3 , d 4 /cntr0, k, reset , x in - ? 0.3 to v dd +0.3 v v o output voltage p0, p1, p2, p3, d 0 ? d 3 , d 4 /cntr0, reset output transistors in cut-off state ? 0.3 to v dd +0.3 v v o output voltage c, x out - ? 0.3 to v dd +0.3 v p d power dissipation ta = 25 c 300 mw t opr operating temperature range - ? 20 to 85 c t stg storage temperature range - ? 40 to 125 c
rev.1.02 may 25, 2007 page 120 of 124 rej03b0179-0102 4571 group recommended operating conditions note 1.the average output current is the average value during 100ms. table 26 recommended operating conditions 1 (ta = ?20 c to 85 c, v dd = 1.8 to 5.5 v, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v dd supply voltage (with a ceramic resonator) f(stck) 6mhz 4 5.5 v f(stck) 4.4mhz 2.7 5.5 f(stck) 2.2mhz 2 5.5 f(stck) 1.1mhz 1.8 5.5 v dd supply voltage (when an external clock is used) f(stck) 4.8mhz 4 5.5 v f(stck) 3.2mhz 2.7 5.5 f(stck) 1.6mhz 2 5.5 f(stck) 0.8mhz 1.8 5.5 v ram ram back-up voltage (at ram back-up) 1.6 5.5 v v ss supply voltage 0v v ih ?h? level input voltage p0, p1, p2, p3, d 0 ? d 4 , k 0.8v dd v dd v x in 0.7v dd v dd reset , int0, int1 0.85v dd v dd cntr0 0.85v dd v dd v il ?l? level input voltage p0, p1, p2, p3, d 0 ? d 4 , k 0 0.3v dd ma x in 00.3v dd reset , int0, int1 00.3v dd cntr0 0 0.15v dd i oh(peak) ?h? level peak output current p3, d 0 ? d 3 v dd = 5v ? 20 ma v dd = 3v ? 10 c, cntr1 v dd = 5v ? 30 v dd = 3v ? 15 i oh(avg) ?h? level average output current (note 1) p3, d 0 ? d 3 v dd = 5v ? 10 ma v dd = 3v ? 5 c, cntr1 v dd = 5v ? 15 v dd = 3v ? 7 i ol(peak) ?l? level peak output current p0, p1, p2, p3, d 0 ? d 4 , c, reset , cntr0, cntr1, v dd = 5v 24 ma v dd = 3v 12 i ol(avg) ?l? level average output current (note 1) p0, p1, p2, p3, d 0 ? d 4 , c, reset , cntr0, cntr1, v dd = 5v 12 ma v dd = 3v 6 i oh(avg) ?h? level total average current p3, d 0 ? d 3 , c, cntr1 ? 30 ma i ol(avg) ?l? level total average current p0, p1 0 , p1 1 , reset 30 ma p1 0 , p1 1 , p2, p3, d 0 ? d 4 , c, cntr0, cntr1 30
rev.1.02 may 25, 2007 page 121 of 124 rej03b0179-0102 4571 group note 1. if the rising time exceeds the maximum rating value, connect a capacitor between the reset pin and vss at the shortest distance, and input ?l? level to reset pin until the value of supply volt age reaches the minimum operating voltage. fig 71. system clock (stck) operating condition map table 27 recommended operating conditions 2 (ta = ?20 c to 85 c, v dd = 1.8 to 5.5 v, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. f(x in ) oscillation frequency (with a ceramic resonator) through mode v dd = 4.0 v to 5.5 v 6 mhz v dd = 2.7 v to 5.5 v 4.4 v dd = 2.0 v to 5.5 v 2.2 v dd = 1.8 v to 5.5 v 1.1 internal frequency divided by 2 v dd = 2.7 v to 5.5 v 6 v dd = 2.0 v to 5.5 v 4.4 v dd = 1.8 v to 5.5 v 2.2 internal frequency divided by 4, 8 v dd = 2.0 v to 5.5 v 6 v dd = 1.8 v to 5.5 v 4.4 f(x in ) oscillation frequency (with an external clock input) through mode v dd = 4.0 v to 5.5 v 4.8 mhz v dd = 2.7 v to 5.5 v 3.2 v dd = 2.0 v to 5.5 v 1.6 v dd = 1.8 v to 5.5 v 0.8 internal frequency divided by 2 v dd = 2.7 v to 5.5 v 4.8 v dd = 2.0 v to 5.5 v 3.2 v dd = 1.8 v to 5.5 v 1.6 internal frequency divided by 4, 8 v dd = 2.0 v to 5.5 v 4.8 v dd = 1.8 v to 5.5 v 3.2 f(cntr) timer external input frequency cntr0, cntr1 f(stck)/6 hz tw(cntr) timer external input period (?h? and ?l? pulse width) cntr0, cntr1 3/f(stck) s t pon power-on reset circuit valid supply voltage rising time (note 1) v dd = 0 1.8v 100 s 1.1 2.2 4.4 6 1.8 2 2.7 4 5.5 recommended operating conditions with a ceramic resonator f(stck) [mhz] v dd [v] 0.8 1.6 3.2 4.8 1.8 2 2.7 4 5.5 recommended operating conditions at external clock oscillation f(stck) [mhz] v dd [v]
rev.1.02 may 25, 2007 page 122 of 124 rej03b0179-0102 4571 group electrical characteristics note 1.the voltage drop detection circuit operation current (i rst ) is added. table 28 electrical charac teristics 1 (ta = ?20 c to 85 c, v dd = 1.8 to 5.5 v, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v oh ?h? level output voltage p3, d 0 ? d 4 v dd = 5v i oh = ? 10ma 3 v cntr0 i oh = ? 3ma 4.1 v dd = 3v i oh = ? 5ma 2.1 i oh = ? 1ma 2.4 v oh ?h? level output voltage c cntr1 v dd = 5v i ol = ? 20ma 3 v i ol = ? 6ma 4.1 v dd = 3v i ol = ? 10ma 2.1 i ol = ? 3ma 2.4 v ol ?l? level output voltage p0, p1, p2, p3, d 0 ? d 4 reset , c, cntr0, cntr1 v dd = 5v i ol = 15ma 2 v i ol = 5ma 0.9 v dd = 3v i ol = 9ma 1.4 i ol = 3ma 0.9 i ih ?h? level input current p0, p1, p2, p3, d 0 ? d 4 , k reset , int0, int1 cntr0 v i = v dd 2 a i il ?l? level input current p0, p1, p2, p3, d 0 ? d 4 , k reset , int0, int1 cntr0 v i = 0v p0, p1, p2 no pull-up ? 2 a r pu pull-up resistor value p0, p1, p2 reset v i = 0v v dd = 5v 30 60 125 k ? v dd = 3v 50 120 250 v t+ ? v t ? hysteresis reset , int0, int1 v dd = 5v 1 v v dd = 3v 0.4 v t+ ? v t ? hysteresis cntr0 v dd = 5v 0.2 v v dd = 3v 0.2 i dd supply current at active mode (with a ceramic resonator) (note 1) v dd = 5v f(x in ) = 6mhz f(ring) = stop f(stck) = f(x in )/8 1.2 2.4 ma f(stck) = f(x in )/4 1.3 2.6 f(stck) = f(x in )/2 1.6 3.2 f(stck) = f(x in )2.24.4 v dd = 3v f(x in ) = 4mhz f(ring) = stop f(stck) = f(x in )/8 0.3 0.6 ma f(stck) = f(x in )/4 0.4 0.8 f(stck) = f(x in )/2 0.6 1.2 f(stck) = f(x in )0.81.6 at ram back-up mode (pof instruction execution) ta = 2 5 c0.13 a v dd = 5v 10 v dd = 3v 6
rev.1.02 may 25, 2007 page 123 of 124 rej03b0179-0102 4571 group voltage drop detection circuit characteristics note 1.the detection voltage (v rst ? ) is defined as the voltage when reset occurs when the supply voltage (v dd ) is falling. note 2.the detection voltage (v rst +) is defined as the voltage when reset is released when the supply voltage (v dd ) is rising from reset occurs. note 3.when the supply voltage goes lower than the detection voltage (v int ), the voltage drop detection circuit interrupt request flag (vdf) is set to ?1?. note 4.i rst is added to i dd (power current). note 5.the detection time (t rst ) is defined as the time until rese t occurs when the supply voltage (v dd ) is falling to [v rst - ? 0.1v]. basic timing diagram table 29 voltage drop detection circuit characteristics (ta = ?20 c to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v rst - detection voltage (reset occurs) (note 1) ta = 2 5 c1.65v ? 20 c ta < 0 c1.62.2 0 c ta < 50 c1.32.1 50 c ta 85 c1.11.8 v rst+ detection voltage (reset release) (note 2) ta = 2 5 c1.75v ? 20 c ta < 0 c1.72.3 0 c ta < 50 c1.42.2 50 c ta 85 c1.21.9 v int detection voltage (interrupt occurs) (note 3) ta = 2 5 c1.85v ? 20 c ta < 0 c1.82.4 0 c ta < 50 c1.52.3 50 c ta 85 c1.32.2 v rst + ? v rst - detection voltage hysteresis 0.1 v i rst voltage drop detection circuit operation current (note 4) v dd = 5v 40 80 a v dd = 3v 20 40 v dd = 1.65v 7 15 t rst detection time (note 5) v dd (v rst - ? 0.1v) 0.2 1.2 ms system clock stck port output d 0 to d 4 p0 0 to p0 3 p1 0 to p1 3 p2 0 ,p2 1 p3 0 ,p3 1 ,c port input d 0 to d 4 p0 0 to p0 3 p1 0 to p1 3 p2 0 ,p2 1 p3 0 ,p3 1 ,k interrupt input int0, int1 parameter pin name machine cycle mi mi + 1
4571 group rev.1.02 may 25, 2007 page 124 of 124 rej03b0179-0102 package outline f 1 12 13 24 * 2 * 1 * 3 index mark y e h e e b p d a c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. a 1 0 0.1 0.2 previous code jeita package code renesas code prsp0024ga-a 24p2q-a mass[typ.] 0.2g p-ssop24-5.3x10.1-0.80 0.25 0.2 0.18 0.45 0.35 0.3 max nom min dimension in millimeters symbol reference 10.2 10.1 10.0 d 5.4 5.3 5.2 e 1.8 a 2 8.1 7.8 7.5 2.1 a 0.8 0.6 0.4 l 8 0 c 0.8 e 0.10 y h e b p 0.65 0.95
(1/1) revision history 4571 group datasheet rev. date description page summary 1.00 feb. 20, 2006 ?
notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas product s for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of t he use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application ci rcuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attentio n to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding th e suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of h uman injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion co ntrol, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a r enesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to us e renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 7. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .7.0

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